Xilinx DDR2 memory interface debug code, frequency 167Mhz, embedded code CHIPSCORP.

Xil3SD1800A_MIG_ISIM_vlog_v92
.............................\ddr2_32Mx32_vlog
.............................\................\ddr2_32Mx32
.............................\................\...........\docs
.............................\................\...........\....\adr_cntrl_timing_0.xls
.............................\................\...........\....\read_data_timing_0.xls
.............................\................\...........\....\write_data_timing_0.xls
.............................\................\...........\example_design
.............................\................\...........\..............\datasheet.txt
.............................\................\...........\..............\log.txt
.............................\................\...........\..............\mig.prj
.............................\................\...........\..............\par
.............................\................\...........\..............\...\automake.log
.............................\................\...........\..............\...\create_ise.bat
.............................\................\...........\..............\...\ddr2_32Mx32.ucf
.............................\................\...........\..............\...\ddr2_32Mx32_summary.html
.............................\................\...........\..............\...\ddr2_speedway.bat
.............................\................\...........\..............\...\ddr2_speedway.ise
.............................\................\...........\..............\...\ddr2_speedway.ise_ISE_Backup
.............................\................\...........\..............\...\ddr2_speedway.restore
.............................\................\...........\..............\...\example.xwv
.............................\................\...........\..............\...\ise_flow.bat
.............................\................\...........\..............\...\ise_run.txt
.............................\................\...........\..............\...\isim
.............................\................\...........\..............\...\....\temp
.............................\................\...........\..............\...\....\....\hdllib.ref
.............................\................\...........\..............\...\....\....\hdpdeps.ref
.............................\................\...........\..............\...\....\....\vlg02
.............................\................\...........\..............\...\....\....\.....\ddr2__32_mx32__infrastructure.bin
.............................\................\...........\..............\...\....\....\vlg0D
.............................\................\...........\..............\...\....\....\.....\ddr2__32_mx32__infrastructure__iobs__0.bin
.............................\................\...........\..............\...\....\....\vlg0F
.............................\................\...........\..............\...\....\....\.....\ddr2__32_mx32__dqs__delay.bin
.............................\................\...........\..............\...\....\....\vlg10
.............................\................\...........\..............\...\....\....\.....\ddr2__32_mx32__controller__iobs__0.bin
.............................\................\...........\..............\...\....\....\vlg14
.............................\................\...........\..............\...\....\....\.....\ddr2__32_mx32__controller__0.bin
.............................\................\...........\..............\...\....\....\vlg18
.............................\................\...........\..............\...\....\....\.....\ddr2__32_mx32__addr__gen__0.bin
.............................\................\...........\..............\...\....\....\vlg19
.............................\................\...........\..............\...\....\....\.....\ddr2__32_mx32__fifo__0__wr__en__0.bin
.............................\................\...........\..............\...\....\....\vlg1B
.............................\................\...........\..............\...\....\....\.....\ddr2__32_mx32__cal__ctl.bin
............................

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