Direct digital frequency synthesizer, based on the VHDL language, in qartus II achieved a successful download debugging

dds
...\5120.mif
...\cmp_state.ini
...\db
...\..\add_sub_9ce.tdf
...\..\add_sub_vge.tdf
...\..\altsyncram_3gm.tdf
...\..\altsyncram_amp.tdf
...\..\altsyncram_dso.tdf
...\..\dds.asm.qmsg
...\..\dds.cmp.cdb
...\..\dds.cmp.ddb
...\..\dds.cmp.hdb
...\..\dds.cmp.rdb
...\..\dds.cmp.tdb
...\..\dds.cmp0.ddb
...\..\dds.db_info
...\..\dds.eco.cdb
...\..\dds.eda.qmsg
...\..\dds.eds_overflow
...\..\dds.fit.qmsg
...\..\dds.fnsim.cdb
...\..\dds.fnsim.hdb
...\..\dds.hier_info
...\..\dds.hif
...\..\dds.icc
...\..\dds.map.cdb
...\..\dds.map.hdb
...\..\dds.map.qmsg
...\..\dds.pre_map.cdb
...\..\dds.pre_map.hdb
...\..\dds.psp
...\..\dds.rtlv.hdb
...\..\dds.rtlv_sg.cdb
...\..\dds.rtlv_sg_swap.cdb
...\..\dds.sgdiff.cdb
...\..\dds.sgdiff.hdb
...\..\dds.sim.hdb
...\..\dds.sim.qmsg
...\..\dds.sim.rdb
...\..\dds.sim.vwf
...\..\dds.sld_design_entry.sci
...\..\dds.sld_design_entry_dsc.sci
...\..\dds.syn_hier_info
...\..\dds.tan.qmsg
...\..\dds_cmp.qrpt
...\..\dds_sim.qrpt
...\dd.tdf
...\dds.asm.rpt
...\dds.bdf
...\dds.done
...\dds.eda.rpt
...\dds.fit.eqn
...\dds.fit.rpt
...\dds.fit.summary
...\dds.flow.rpt
...\dds.hex
...\dds.map.eqn
...\dds.map.rpt
...\dds.map.summary
...\dds.pin
...\dds.pof
...\dds.qpf
...\dds.qsf
...\dds.qws
...\dds.sim.rpt
...\dds.sof
...\dds.tan.rpt
...\dds.tan.summary
...\dds.vwf
...\lpm_add_sub0.bsf
...\lpm_add_sub0.v

...\lpm_add_sub0_waveforms.html
...\lpm_dff0.bsf
...\lpm_dff0.v
...\lpm_dff1.bsf
...\lpm_dff1.v
...\lpm_rom0.bsf
...\lpm_rom0.v
...\quartus_nativelink_simulation.log
...\serv_req_info.txt
...\simulation
...\..........\modelsim
...\..........\........\dds.vo
...\..........\........\dds_modelsim.xrf
...\..........\........\dds_v.sdo
...\undo_redo.txt
...\Waveform1.vwf
...\Waveform2.vwf

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