Image Edge Detection of Verilog realize that can accurately detect image edge

sobel
.....\CCD_Capture.v
.....\db
.....\..\DE2_CCD.db_info
.....\..\DE2_CCD.eco.cdb
.....\..\DE2_CCD.sld_design_entry.sci
.....\DE2_CCD.asm.rpt
.....\DE2_CCD.cdf
.....\DE2_CCD.done
.....\DE2_CCD.dpf
.....\DE2_CCD.fit.eqn
.....\DE2_CCD.fit.rpt
.....\DE2_CCD.fit.smsg
.....\DE2_CCD.fit.summary
.....\DE2_CCD.flow.rpt
.....\DE2_CCD.map.eqn
.....\DE2_CCD.map.rpt
.....\DE2_CCD.map.smsg
.....\DE2_CCD.map.summary
.....\DE2_CCD.pin
.....\DE2_CCD.pof
.....\DE2_CCD.qpf
.....\DE2_CCD.qsf
.....\DE2_CCD.qsf.bak
.....\DE2_CCD.qws
.....\DE2_CCD.sof
.....\DE2_CCD.srf
.....\DE2_CCD.tan.rpt
.....\DE2_CCD.tan.summary
.....\DE2_CCD.v
.....\DE2_CCD.v.bak
.....\DE2_CCD_assignment_defaults.qdf
.....\I2C_CCD_Config.v
.....\I2C_CCD_Config.v.bak
.....\I2C_Controller.v
.....\linetest.v
.....\linetest_bb.v
.....\Line_Buffer.v
.....\Mirror_Col.v
.....\Mirror_Col.v.bak
.....\RAW2RGB.v
.....\refImageExtractor.v
.....\Reset_Delay.v
.....\Sdram_Control_4Port
.....\...................\command.v
.....\...................\control_interface.v
.....\...................\Sdram_Control_4Port.v
.....\...................\Sdram_FIFO.v
.....\...................\Sdram_Params.h
.....\...................\Sdram_PLL.v
.....\...................\sdr_data_path.v
.....\SEG7_LUT.v
.....\SEG7_LUT_8.v
.....\shitbox.v
.....\sobel.v
.....\sobel.v.bak
.....\sopc_builder_debug_log.txt
.....\Stack_RAM.v
.....\VGA_Audio_PLL.bsf
.....\VGA_Audio_PLL.ppf
.....\VGA_Audio_PLL.v

.....\VGA_Audio_PLL_waveforms.html
.....\VGA_Controller.v
.....\VGA_Param.h

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