The use of VHDL language to achieve, altera s cyclone chip digital signal modulation and demodulation functions 2psk

psk
...\adder7b.vhd
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...\DATA
...\....\LUT10X10.HEX
...\....\LUT10X10.MIF
...\db
...\..\altsyncram_0sj2.tdf
...\..\altsyncram_5mp.tdf
...\..\altsyncram_6v51.tdf
...\..\altsyncram_hmi2.tdf
...\..\altsyncram_hq21.tdf
...\..\altsyncram_kna2.tdf
...\..\altsyncram_qqs.tdf
...\..\cmpr_fnh.tdf
...\..\cntr_5af.tdf
...\..\cntr_dkf.tdf
...\..\cntr_ebg.tdf
...\..\cntr_fgh.tdf
...\..\cntr_fhe.tdf
...\..\dds.asm.qmsg
...\..\dds.cbx.xml
...\..\dds.cmp.cdb
...\..\dds.cmp.hdb
...\..\dds.cmp.kpt
...\..\dds.cmp.logdb
...\..\dds.cmp.rdb
...\..\dds.cmp.tdb
...\..\dds.cmp0.ddb
...\..\dds.dbp
...\..\dds.db_info
...\..\dds.eco.cdb
...\..\dds.eds_overflow
...\..\dds.fit.qmsg
...\..\dds.hier_info
...\..\dds.hif
...\..\dds.map.cdb
...\..\dds.map.hdb
...\..\dds.map.logdb
...\..\dds.map.qmsg
...\..\dds.pre_map.cdb
...\..\dds.pre_map.hdb
...\..\dds.psp
...\..\dds.pss
...\..\dds.rtlv.hdb
...\..\dds.rtlv_sg.cdb
...\..\dds.rtlv_sg_swap.cdb
...\..\dds.sgdiff.cdb
...\..\dds.sgdiff.hdb
...\..\dds.signalprobe.cdb
...\..\dds.sim.hdb
...\..\dds.sim.qmsg
...\..\dds.sim.rdb
...\..\dds.sim.vwf
...\..\dds.sld_design_entry.sci
...\..\dds.sld_design_entry_dsc.sci
...\..\dds.syn_hier_info
...\..\dds.tan.qmsg
...\..\dds_cmp.qrpt
...\..\dds_sim.qrpt
...\..\decode_9ie.tdf
...\..\decode_ogi.tdf
...\..\wed.zsf
...\dds.asm.rpt
...\DDS.CDF
...\dds.done
...\dds.fit.eqn
...\dds.fit.rpt
...\dds.fit.smsg
...\dds.fit.summary
...\dds.flow.rpt
...\dds.map.eqn
...\dds.map.rpt
...\dds.map.summary
...\DDS.PIN
...\dds.pof
...\DDS.QPF
...\DDS.QSF
...\DDS.QWS
...\dds.sim.rpt
...\DDS.SOF
...\dds.tan.rpt
...\dds.tan.summary
...\dds.vhd
...\dds.vwf
...\DDS1.VHD
...\dds_assignment_defaults.qdf
...\fangbo.vhd
...\pl_dpsk2.vhd
...\ps7.vhd
...\README
...\......\GW48使用readme.txt
...\reg7b.vhd
...\serv_req_info.txt
...\sin7.mif
...\SIN_ROM.BSF
...\SIN_ROM.VHD
...\sopc_builder_debug_log.txt

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