Realize using Verilog ALU, realize a variety of arithmetic operations, logic operations, shift operations, etc.

3
.\alu.asm.rpt
.\alu.done
.\alu.fit.rpt
.\alu.fit.smsg
.\alu.fit.summary
.\alu.flow.rpt
.\alu.map.rpt
.\alu.map.summary
.\alu.pin
.\alu.pof
.\alu.qpf
.\alu.qsf
.\alu.qws
.\alu.sim.rpt
.\alu.sof
.\alu.tan.rpt
.\alu.tan.summary
.\alu.v
.\alu.v.bak
.\alu.vwf
.\db
.\..\alu.asm.qmsg
.\..\alu.cbx.xml
.\..\alu.cmp.ecobp
.\..\alu.cmp.rdb
.\..\alu.cmp0.ddb
.\..\alu.cmp_bb.cdb
.\..\alu.cmp_bb.hdb
.\..\alu.cmp_bb.logdb
.\..\alu.cmp_bb.rcf
.\..\alu.dbp
.\..\alu.db_info
.\..\alu.eco.cdb
.\..\alu.eds_overflow
.\..\alu.fit.qmsg
.\..\alu.hier_info
.\..\alu.hif
.\..\alu.map.ecobp
.\..\alu.map.qmsg
.\..\alu.map_bb.logdb
.\..\alu.pre_map.cdb
.\..\alu.pre_map.hdb
.\..\alu.psp
.\..\alu.pss
.\..\alu.rtlv.hdb
.\..\alu.rtlv_sg.cdb
.\..\alu.rtlv_sg_swap.cdb
.\..\alu.sgdiff.cdb
.\..\alu.sgdiff.hdb
.\..\alu.sim.cvwf
.\..\alu.sim.hdb
.\..\alu.sim.qmsg
.\..\alu.sim.rdb
.\..\alu.sld_design_entry.sci
.\..\alu.sld_design_entry_dsc.sci
.\..\alu.syn_hier_info
.\..\alu.tan.qmsg
.\..\alu.tis_db_list.ddb
.\..\prev_cmp_alu.asm.qmsg
.\..\prev_cmp_alu.fit.qmsg
.\..\prev_cmp_alu.map.qmsg
.\..\prev_cmp_alu.qmsg
.\..\prev_cmp_alu.sim.qmsg
.\..\prev_cmp_alu.tan.qmsg
.\..\wed.wsf
.\pc.v
.\pc.v.bak
.\regfile.v
.\regfile.v.bak
.\Verilog2.v

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