With GMII interface and feature ARP protocol Gigabit Ethernet controller. After Xilinx SPATAN-III FPGA verification, Verilog description

arp.v
cache_control.v
content.edn
content.sym
content.v
content.veo
content.vhd
content.vho
content.xco
content.xcp
coregen.prj
data.v
data_fifo.v
encapsule.sym
encapsule.v
ethernet.sym
ethernet.v
gigarecv.v
gigatran.v
packet_cache.edn
packet_cache.sym
packet_cache.v
packet_cache.veo
packet_cache.vhd
packet_cache.vho
packet_cache.xco
packet_cache.xcp
pack_control.v
protocol.v
ram.edn
ram.sym
ram.v
ram.veo
ram.vhd
ram.vho
ram.xco
ram.xcp
receive.v
rxdcache.edn
rxdcache.sym
rxdcache.v
rxdcache.veo
rxdcache.vhd
rxdcache.vho
rxdcache.xco
rxdcache.xcp
r_arp.v
r_ip.v
r_netlayer.v
send.v
transmit.v
tx_fifo.v
t_netlayer.v
udp.v

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