Xilinx-modelsim-library Xilinx modelsim simulation

Xilinx-modelsim-library

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Update : 2008-10-13
Size : 30.7mb
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Author ：杨俊涛
About ：杨俊涛
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Introduction - If you have any usage issues, please Google them yourself
Xilinx modelsim simulation library! There are many libraries, vlog or VHDL programming a lot of good source code can shear!
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Packet : 69491751xilinx-modelsim-library.rar filelist
xilinx
xilinx\verilog
xilinx\verilog\simprims_ver
xilinx\verilog\simprims_ver\_info
xilinx\verilog\simprims_ver\@x_@a@n@d16
xilinx\verilog\simprims_ver\@x_@a@n@d16\_primary.vhd
xilinx\verilog\simprims_ver\@x_@a@n@d16\verilog.asm
xilinx\verilog\simprims_ver\@x_@a@n@d16\_primary.dat
xilinx\verilog\simprims_ver\@x_@a@n@d2
xilinx\verilog\simprims_ver\@x_@a@n@d2\_primary.vhd
xilinx\verilog\simprims_ver\@x_@a@n@d2\verilog.asm
xilinx\verilog\simprims_ver\@x_@a@n@d2\_primary.dat
xilinx\verilog\simprims_ver\@x_@a@n@d3
xilinx\verilog\simprims_ver\@x_@a@n@d3\_primary.vhd
xilinx\verilog\simprims_ver\@x_@a@n@d3\verilog.asm
xilinx\verilog\simprims_ver\@x_@a@n@d3\_primary.dat
xilinx\verilog\simprims_ver\@x_@a@n@d32
xilinx\verilog\simprims_ver\@x_@a@n@d32\_primary.vhd
xilinx\verilog\simprims_ver\@x_@a@n@d32\verilog.asm
xilinx\verilog\simprims_ver\@x_@a@n@d32\_primary.dat
xilinx\verilog\simprims_ver\@x_@a@n@d4
xilinx\verilog\simprims_ver\@x_@a@n@d4\_primary.vhd
xilinx\verilog\simprims_ver\@x_@a@n@d4\verilog.asm
xilinx\verilog\simprims_ver\@x_@a@n@d4\_primary.dat
xilinx\verilog\simprims_ver\@x_@a@n@d5
xilinx\verilog\simprims_ver\@x_@a@n@d5\_primary.vhd
xilinx\verilog\simprims_ver\@x_@a@n@d5\verilog.asm
xilinx\verilog\simprims_ver\@x_@a@n@d5\_primary.dat
xilinx\verilog\simprims_ver\@x_@a@n@d6
xilinx\verilog\simprims_ver\@x_@a@n@d6\_primary.vhd
xilinx\verilog\simprims_ver\@x_@a@n@d6\verilog.asm
xilinx\verilog\simprims_ver\@x_@a@n@d6\_primary.dat
xilinx\verilog\simprims_ver\@x_@a@n@d7
xilinx\verilog\simprims_ver\@x_@a@n@d7\_primary.vhd
xilinx\verilog\simprims_ver\@x_@a@n@d7\verilog.asm
xilinx\verilog\simprims_ver\@x_@a@n@d7\_primary.dat
xilinx\verilog\simprims_ver\@x_@a@n@d8
xilinx\verilog\simprims_ver\@x_@a@n@d8\_primary.vhd
xilinx\verilog\simprims_ver\@x_@a@n@d8\verilog.asm
xilinx\verilog\simprims_ver\@x_@a@n@d8\_primary.dat
xilinx\verilog\simprims_ver\@x_@b@p@a@d
xilinx\verilog\simprims_ver\@x_@b@p@a@d\_primary.vhd
xilinx\verilog\simprims_ver\@x_@b@p@a@d\verilog.asm
xilinx\verilog\simprims_ver\@x_@b@p@a@d\_primary.dat
xilinx\verilog\simprims_ver\@x_@b@u@f
xilinx\verilog\simprims_ver\@x_@b@u@f\_primary.vhd
xilinx\verilog\simprims_ver\@x_@b@u@f\verilog.asm
xilinx\verilog\simprims_ver\@x_@b@u@f\_primary.dat
xilinx\verilog\simprims_ver\@x_@c@k@b@u@f
xilinx\verilog\simprims_ver\@x_@c@k@b@u@f\_primary.vhd
xilinx\verilog\simprims_ver\@x_@c@k@b@u@f\verilog.asm
xilinx\verilog\simprims_ver\@x_@c@k@b@u@f\_primary.dat
xilinx\verilog\simprims_ver\@x_@c@l@k@d@l@l
xilinx\verilog\simprims_ver\@x_@c@l@k@d@l@l\_primary.vhd
xilinx\verilog\simprims_ver\@x_@c@l@k@d@l@l\verilog.asm
xilinx\verilog\simprims_ver\@x_@c@l@k@d@l@l\_primary.dat
xilinx\verilog\simprims_ver\@x_@c@l@k@d@l@l@e
xilinx\verilog\simprims_ver\@x_@c@l@k@d@l@l@e\_primary.vhd
xilinx\verilog\simprims_ver\@x_@c@l@k@d@l@l@e\verilog.asm
xilinx\verilog\simprims_ver\@x_@c@l@k@d@l@l@e\_primary.dat
xilinx\verilog\simprims_ver\@x_@c@l@k_@d@i@v
xilinx\verilog\simprims_ver\@x_@c@l@k_@d@i@v\_primary.vhd
xilinx\verilog\simprims_ver\@x_@c@l@k_@d@i@v\verilog.asm
xilinx\verilog\simprims_ver\@x_@c@l@k_@d@i@v\_primary.dat
xilinx\verilog\simprims_ver\@x_@d@c@m
xilinx\verilog\simprims_ver\@x_@d@c@m\_primary.vhd
xilinx\verilog\simprims_ver\@x_@d@c@m\verilog.asm
xilinx\verilog\simprims_ver\@x_@d@c@m\_primary.dat
xilinx\verilog\simprims_ver\@x_@f@d@d
xilinx\verilog\simprims_ver\@x_@f@d@d\_primary.vhd
xilinx\verilog\simprims_ver\@x_@f@d@d\verilog.asm
xilinx\verilog\simprims_ver\@x_@f@d@d\_primary.dat
xilinx\verilog\simprims_ver\ffsrced
xilinx\verilog\simprims_ver\ffsrced\_primary.vhd
xilinx\verilog\simprims_ver\ffsrced\verilog.asm
xilinx\verilog\simprims_ver\ffsrced\_primary.dat
xilinx\verilog\simprims_ver\@x_@f@f
xilinx\verilog\simprims_ver\@x_@f@f\_primary.vhd
xilinx\verilog\simprims_ver\@x_@f@f\verilog.asm
xilinx\verilog\simprims_ver\@x_@f@f\_primary.dat
xilinx\verilog\simprims_ver\ffsrce
xilinx\verilog\simprims_ver\ffsrce\_primary.vhd
xilinx\verilog\simprims_ver\ffsrce\verilog.asm
xilinx\verilog\simprims_ver\ffsrce\_primary.dat
xilinx\verilog\simprims_ver\@x_@g@t
xilinx\verilog\simprims_ver\@x_@g@t\_primary.vhd
xilinx\verilog\simprims_ver\@x_@g@t\verilog.asm
xilinx\verilog\simprims_ver\@x_@g@t\_primary.dat
xilinx\verilog\simprims_ver\@x_@i@b@u@f@d@s
xilinx\verilog\simprims_ver\@x_@i@b@u@f@d@s\_primary.vhd
xilinx\verilog\simprims_ver\@x_@i@b@u@f@d@s\verilog.asm
xilinx\verilog\simprims_ver\@x_@i@b@u@f@d@s\_primary.dat
xilinx\verilog\simprims_ver\@x_@i@n@v
xilinx\verilog\simprims_ver\@x_@i@n@v\_primary.vhd
xilinx\verilog\simprims_ver\@x_@i@n@v\verilog.asm
xilinx\verilog\simprims_ver\@x_@i@n@v\_primary.dat
xilinx\verilog\simprims_ver\@x_@i@p@a@d
xilinx\verilog\simprims_ver\@x_@i@p@a@d\_primary.vhd
xilinx\verilog\simprims_ver\@x_@i@p@a@d\verilog.asm
xilinx\verilog\simprims_ver\@x_@i@p@a@d\_primary.dat
xilinx\verilog\simprims_ver\@x_@k@e@e@p@e@r
xilinx\verilog\simprims_ver\@x_@k@e@e@p@e@r\_primary.vhd
xilinx\verilog\simprims_ver\@x_@k@e@e@p@e@r\verilog.asm
xilinx\verilog\simprims_ver\@x_@k@e@e@p@e@r\_primary.dat
xilinx\verilog\simprims_ver\@x_@l@a@t@c@h
xilinx\verilog\simprims_ver\@x_@l@a@t@c@h\_primary.vhd
xilinx\verilog\simprims_ver\@x_@l@a@t@c@h\verilog.asm
xilinx\verilog\simprims_ver\@x_@l@a@t@c@h\_primary.dat
xilinx\verilog\simprims_ver\latchsr
xilinx\verilog\simprims_ver\latchsr\_primary.vhd
xilinx\verilog\simprims_ver\latchsr\verilog.asm
xilinx\verilog\simprims_ver\latchsr\_primary.dat
xilinx\verilog\simprims_ver\@x_@l@a@t@c@h@e
xilinx\verilog\simprims_ver\@x_@l@a@t@c@h@e\_primary.vhd
xilinx\verilog\simprims_ver\@x_@l@a@t@c@h@e\verilog.asm
xilinx\verilog\simprims_ver\@x_@l@a@t@c@h@e\_primary.dat
xilinx\verilog\simprims_ver\latchsre
xilinx\verilog\simprims_ver\latchsre\_primary.vhd
xilinx\verilog\simprims_ver\latchsre\verilog.asm
xilinx\verilog\simprims_ver\latchsre\_primary.dat
xilinx\verilog\simprims_ver\@x_@l@u@t2
xilinx\verilog\simprims_ver\@x_@l@u@t2\_primary.vhd
xilinx\verilog\simprims_ver\@x_@l@u@t2\verilog.asm
xilinx\verilog\simprims_ver\@x_@l@u@t2\_primary.dat
xilinx\verilog\simprims_ver\x_lut2_mux4
xilinx\verilog\simprims_ver\x_lut2_mux4\_primary.vhd
xilinx\verilog\simprims_ver\x_lut2_mux4\verilog.asm
xilinx\verilog\simprims_ver\x_lut2_mux4\_primary.dat
xilinx\verilog\simprims_ver\@x_@l@u@t3
xilinx\verilog\simprims_ver\@x_@l@u@t3\_primary.vhd
xilinx\verilog\simprims_ver\@x_@l@u@t3\verilog.asm
xilinx\verilog\simprims_ver\@x_@l@u@t3\_primary.dat
xilinx\verilog\simprims_ver\x_lut3_mux4
xilinx\verilog\simprims_ver\x_lut3_mux4\_primary.vhd
xilinx\verilog\simprims_ver\x_lut3_mux4\verilog.asm
xilinx\verilog\simprims_ver\x_lut3_mux4\_primary.dat
xilinx\verilog\simprims_ver\@x_@l@u@t4
xilinx\verilog\simprims_ver\@x_@l@u@t4\_primary.vhd
xilinx\verilog\simprims_ver\@x_@l@u@t4\verilog.asm
xilinx\verilog\simprims_ver\@x_@l@u@t4\_primary.dat
xilinx\verilog\simprims_ver\x_lut4_mux4
xilinx\verilog\simprims_ver\x_lut4_mux4\_primary.vhd
xilinx\verilog\simprims_ver\x_lut4_mux4\verilog.asm
xilinx\verilog\simprims_ver\x_lut4_mux4\_primary.dat
xilinx\verilog\simprims_ver\@x_@l@u@t5
xilinx\verilog\simprims_ver\@x_@l@u@t5\_primary.vhd
xilinx\verilog\simprims_ver\@x_@l@u@t5\verilog.asm
xilinx\verilog\simprims_ver\@x_@l@u@t5\_primary.dat
xilinx\verilog\simprims_ver\x_lut5_mux4
xilinx\verilog\simprims_ver\x_lut5_mux4\_primary.vhd
xilinx\verilog\simprims_ver\x_lut5_mux4\verilog.asm
xilinx\verilog\simprims_ver\x_lut5_mux4\_primary.dat
xilinx\verilog\simprims_ver\@x_@l@u@t6
xilinx\verilog\simprims_ver\@x_@l@u@t6\_primary.vhd
xilinx\verilog\simprims_ver\@x_@l@u@t6\verilog.asm
xilinx\verilog\simprims_ver\@x_@l@u@t6\_primary.dat
xilinx\verilog\simprims_ver\x_lut6_mux4
xilinx\verilog\simprims_ver\x_lut6_mux4\_primary.vhd
xilinx\verilog\simprims_ver\x_lut6_mux4\verilog.asm
xilinx\verilog\simprims_ver\x_lut6_mux4\_primary.dat
xilinx\verilog\simprims_ver\@x_@l@u@t7
xilinx\verilog\simprims_ver\@x_@l@u@t7\_primary.vhd
xilinx\verilog\simprims_ver\@x_@l@u@t7\verilog.asm
xilinx\verilog\simprims_ver\@x_@l@u@t7\_primary.dat
xilinx\verilog\simprims_ver\x_lut7_mux4
xilinx\verilog\simprims_ver\x_lut7_mux4\_primary.vhd
xilinx\verilog\simprims_ver\x_lut7_mux4\verilog.asm
xilinx\verilog\simprims_ver\x_lut7_mux4\_primary.dat
xilinx\verilog\simprims_ver\@x_@l@u@t8
xilinx\verilog\simprims_ver\@x_@l@u@t8\_primary.vhd
xilinx\verilog\simprims_ver\@x_@l@u@t8\verilog.asm
xilinx\verilog\simprims_ver\@x_@l@u@t8\_primary.dat
xilinx\verilog\simprims_ver\x_lut8_mux4
xilinx\verilog\simprims_ver\x_lut8_mux4\_primary.vhd
xilinx\verilog\simprims_ver\x_lut8_mux4\verilog.asm
xilinx\verilog\simprims_ver\x_lut8_mux4\_primary.dat
xilinx\verilog\simprims_ver\@x_@m@u@l@t18@x18
xilinx\verilog\simprims_ver\@x_@m@u@l@t18@x18\_primary.vhd
xilinx\verilog\simprims_ver\@x_@m@u@l@t18@x18\verilog.asm
xilinx\verilog\simprims_ver\@x_@m@u@l@t18@x18\_primary.dat
xilinx\verilog\simprims_ver\@x_@m@u@l@t18@x18@s
xilinx\verilog\simprims_ver\@x_@m@u@l@t18@x18@s\_primary.vhd
xilinx\verilog\simprims_ver\@x_@m@u@l@t18@x18@s\verilog.asm
xilinx\verilog\simprims_ver\@x_@m@u@l@t18@x18@s\_primary.dat
xilinx\verilog\simprims_ver\@x_@m@u@x2
xilinx\verilog\simprims_ver\@x_@m@u@x2\_primary.vhd
xilinx\verilog\simprims_ver\@x_@m@u@x2\verilog.asm
xilinx\verilog\simprims_ver\@x_@m@u@x2\_primary.dat
xilinx\verilog\simprims_ver\mux
xilinx\verilog\simprims_ver\mux\_primary.vhd
xilinx\verilog\simprims_ver\mux\verilog.asm
xilinx\verilog\simprims_ver\mux\_primary.dat
xilinx\verilog\simprims_ver\@x_@m@u@x@d@d@r
xilinx\verilog\simprims_ver\@x_@m@u@x@d@d@r\_primary.vhd
xilinx\verilog\simprims_ver\@x_@m@u@x@d@d@r\verilog.asm
xilinx\verilog\simprims_ver\@x_@m@u@x@d@d@r\_primary.dat
xilinx\verilog\simprims_ver\@x_@o@b@u@f@d@s
xilinx\verilog\simprims_ver\@x_@o@b@u@f@d@s\_primary.vhd
xilinx\verilog\simprims_ver\@x_@o@b@u@f@d@s\verilog.asm
xilinx\verilog\simprims_ver\@x_@o@b@u@f@d@s\_primary.dat
xilinx\verilog\simprims_ver\@x_@o@b@u@f@t@d@s
xilinx\verilog\simprims_ver\@x_@o@b@u@f@t@d@s\_primary.vhd
xilinx\verilog\simprims_ver\@x_@o@b@u@f@t@d@s\verilog.asm
xilinx\verilog\simprims_ver\@x_@o@b@u@f@t@d@s\_primary.dat
xilinx\verilog\simprims_ver\@x_@o@n@e
xilinx\verilog\simprims_ver\@x_@o@n@e\_primary.vhd
xilinx\verilog\simprims_ver\@x_@o@n@e\verilog.asm
xilinx\verilog\simprims_ver\@x_@o@n@e\_primary.dat
xilinx\verilog\simprims_ver\@x_@o@p@a@d
xilinx\verilog\simprims_ver\@x_@o@p@a@d\_primary.vhd
xilinx\verilog\simprims_ver\@x_@o@p@a@d\verilog.asm
xilinx\verilog\simprims_ver\@x_@o@p@a@d\_primary.dat
xilinx\verilog\simprims_ver\@x_@o@r16
xilinx\verilog\simprims_ver\@x_@o@r16\_primary.vhd
xilinx\verilog\simprims_ver\@x_@o@r16\verilog.asm
xilinx\verilog\simprims_ver\@x_@o@r16\_primary.dat
xilinx\verilog\simprims_ver\@x_@o@r2
xilinx\verilog\simprims_ver\@x_@o@r2\_primary.vhd
xilinx\verilog\simprims_ver\@x_@o@r2\verilog.asm
xilinx\verilog\simprims_ver\@x_@o@r2\_primary.dat
xilinx\verilog\simprims_ver\@x_@o@r3
xilinx\verilog\simprims_ver\@x_@o@r3\_primary.vhd
xilinx\verilog\simprims_ver\@x_@o@r3\verilog.asm
xilinx\verilog\simprims_ver\@x_@o@r3\_primary.dat
xilinx\verilog\simprims_ver\@x_@o@r32
xilinx\verilog\simprims_ver\@x_@o@r32\_primary.vhd
xilinx\verilog\simprims_ver\@x_@o@r32\verilog.asm
xilinx\verilog\simprims_ver\@x_@o@r32\_primary.dat
xilinx\verilog\simprims_ver\@x_@o@r4
xilinx\verilog\simprims_ver\@x_@o@r4\_primary.vhd
xilinx\verilog\simprims_ver\@x_@o@r4\verilog.asm
xilinx\verilog\simprims_ver\@x_@o@r4\_primary.dat
xilinx\verilog\simprims_ver\@x_@o@r5
xilinx\verilog\simprims_ver\@x_@o@r5\_primary.vhd
xilinx\verilog\simprims_ver\@x_@o@r5\verilog.asm
xilinx\verilog\simprims_ver\@x_@o@r5\_primary.dat
xilinx\verilog\simprims_ver\@x_@o@r6
xilinx\verilog\simprims_ver\@x_@o@r6\_primary.vhd
xilinx\verilog\simprims_ver\@x_@o@r6\verilog.asm
xilinx\verilog\simprims_ver\@x_@o@r6\_primary.dat
xilinx\verilog\simprims_ver\@x_@o@r7
xilinx\verilog\simprims_ver\@x_@o@r7\_primary.vhd
xilinx\verilog\simprims_ver\@x_@o@r7\verilog.asm
xilinx\verilog\simprims_ver\@x_@o@r7\_primary.dat
xilinx\verilog\simprims_ver\@x_@o@r8
xilinx\verilog\simprims_ver\@x_@o@r8\_primary.vhd
xilinx\verilog\simprims_ver\@x_@o@r8\verilog.asm
xilinx\verilog\simprims_ver\@x_@o@r8\_primary.dat
xilinx\verilog\simprims_ver\@x_@p@d
xilinx\verilog\simprims_ver\@x_@p@d\_primary.vhd
xilinx\verilog\simprims_ver\@x_@p@d\verilog.asm
xilinx\verilog\simprims_ver\@x_@p@d\_primary.dat
xilinx\verilog\simprims_ver\@x_@p@p@c405
xilinx\verilog\simprims_ver\@x_@p@p@c405\_primary.vhd
xilinx\verilog\simprims_ver\@x_@p@p@c405\verilog.asm
xilinx\verilog\simprims_ver\@x_@p@p@c405\_primary.dat
xilinx\verilog\simprims_ver\@f@p@g@a_startup
xilinx\verilog\simprims_ver\@f@p@g@a_startup\_primary.vhd
xilinx\verilog\simprims_ver\@f@p@g@a_startup\verilog.asm
xilinx\verilog\simprims_ver\@f@p@g@a_startup\_primary.dat
xilinx\verilog\simprims_ver\@x_@p@u
xilinx\verilog\simprims_ver\@x_@p@u\_primary.vhd
xilinx\verilog\simprims_ver\@x_@p@u\verilog.asm
xilinx\verilog\simprims_ver\@x_@p@u\_primary.dat
xilinx\verilog\simprims_ver\@x_@r@a@m16
xilinx\verilog\simprims_ver\@x_@r@a@m16\_primary.vhd
xilinx\verilog\simprims_ver\@x_@r@a@m16\verilog.asm
xilinx\verilog\simprims_ver\@x_@r@a@m16\_primary.dat
xilinx\verilog\simprims_ver\@x_@r@a@m32
xilinx\verilog\simprims_ver\@x_@r@a@m32\_primary.vhd
xilinx\verilog\simprims_ver\@x_@r@a@m32\verilog.asm
xilinx\verilog\simprims_ver\@x_@r@a@m32\_primary.dat
xilinx\verilog\simprims_ver\@x_@r@a@m@b16_@s1
xilinx\verilog\simprims_ver\@x_@r@a@m@b16_@s1\_primary.vhd
xilinx\verilog\simprims_ver\@x_@r@a@m@b16_@s1\verilog.asm
xilinx\verilog\simprims_ver\@x_@r@a@m@b16_@s1\_primary.dat
xilinx\verilog\simprims_ver\@x_@r@a@m@b16_@s18
xilinx\verilog\simprims_ver\@x_@r@a@m@b16_@s18\_primary.vhd
xilinx\verilog\simprims_ver\@x_@r@a@m@b16_@s18\verilog.asm
xilinx\verilog\simprims_ver\@x_@r@a@m@b16_@s18\_primary.dat
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xilinx\verilog\unisims_ver\@o@o@r2\verilog.asm
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xilinx\verilog\unisims_ver\@o@n@o@r2
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xilinx\verilog\unisims_ver\@o@m@u@x2
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xilinx\verilog\unisims_ver\@o@f@d_@u
xilinx\verilog\unisims_ver\@o@f@d_@u\_primary.vhd
xilinx\verilog\unisims_ver\@o@f@d_@u\verilog.asm
xilinx\verilog\unisims_ver\@o@f@d_@u\_primary.dat
xilinx\verilog\unisims_ver\@o@f@d_@s_24
xilinx\verilog\unisims_ver\@o@f@d_@s_24\_primary.vhd
xilinx\verilog\unisims_ver\@o@f@d_@s_24\verilog.asm
xilinx\verilog\unisims_ver\@o@f@d_@s_24\_primary.dat
xilinx\verilog\unisims_ver\@o@f@d_@s
xilinx\verilog\unisims_ver\@o@f@d_@s\_primary.vhd
xilinx\verilog\unisims_ver\@o@f@d_@s\verilog.asm
xilinx\verilog\unisims_ver\@o@f@d_@s\_primary.dat
xilinx\verilog\unisims_ver\@o@f@d_@f_24
xilinx\verilog\unisims_ver\@o@f@d_@f_24\_primary.vhd
xilinx\verilog\unisims_ver\@o@f@d_@f_24\verilog.asm
xilinx\verilog\unisims_ver\@o@f@d_@f_24\_primary.dat
xilinx\verilog\unisims_ver\@o@f@d_@f@u
xilinx\verilog\unisims_ver\@o@f@d_@f@u\_primary.
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