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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 221kb
  • Downloaded :0次
  • Author :Potossas
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
Altera epm240 the UFM call.
Packet file list
(Preview for download)
MAX_UFM
.......\0000
.......\....\cmp_state.ini
.......\....\db
.......\....\..\Main.asm.qmsg
.......\....\..\Main.cbx.xml
.......\....\..\Main.cmp.cdb
.......\....\..\Main.cmp.hdb
.......\....\..\Main.cmp.rdb
.......\....\..\Main.cmp.tdb
.......\....\..\Main.cmp0.ddb
.......\....\..\Main.db_info
.......\....\..\Main.eco.cdb
.......\....\..\Main.fit.qmsg
.......\....\..\Main.hier_info
.......\....\..\Main.hif
.......\....\..\Main.map.cdb
.......\....\..\Main.map.hdb
.......\....\..\Main.map.qmsg
.......\....\..\Main.pre_map.cdb
.......\....\..\Main.pre_map.hdb
.......\....\..\Main.psp
.......\....\..\Main.rtlv.hdb
.......\....\..\Main.rtlv_sg.cdb
.......\....\..\Main.rtlv_sg_swap.cdb
.......\....\..\Main.sgdiff.cdb
.......\....\..\Main.sgdiff.hdb
.......\....\..\Main.signalprobe.cdb
.......\....\..\Main.sld_design_entry.sci
.......\....\..\Main.sld_design_entry_dsc.sci
.......\....\..\Main.syn_hier_info
.......\....\..\Main.tan.qmsg
.......\....\..\Main_cmp.qrpt
.......\....\Main.asm.rpt
.......\....\Main.cdf
.......\....\Main.done
.......\....\Main.fit.eqn
.......\....\Main.fit.rpt
.......\....\Main.fit.summary
.......\....\Main.flow.rpt
.......\....\Main.map.eqn
.......\....\Main.map.rpt
.......\....\Main.map.summary
.......\....\Main.pin
.......\....\Main.pof
.......\....\Main.qsf
.......\....\Main.tan.rpt
.......\....\Main.tan.summary
.......\....\main.v
.......\....\Main_description.txt
.......\....\MAX_UFM.qpf
.......\....\MAX_UFM.qws
.......\....\text.mif
.......\....\UFM.v
.......\....\ufm_bb.v
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