xilinx ddr3 latest VHDL code through debugging

cntl_ddr3(xilinx)
.................\cntl_ddr3
.................\.........\#ddr_controller2.vhd#
.................\.........\.xhdl3.xref
.................\.........\clock_gen.vhd
.................\.........\cntl_ddr2.vhd
.................\.........\command_statemachine.vhd
.................\.........\counters.vhd
.................\.........\data_statemachine.vhd
.................\.........\ddr_cntl2_wrapper.vhd
.................\.........\ddr_cntl3_wrapper.vhd
.................\.........\ddr_cntl3_wrapper.vhd.bak
.................\.........\ddr_controller2.vhd
.................\.........\ddr_ctrl
.................\.........\........\_info
.................\.........\ddr_ctrl.cr.mti
.................\.........\ddr_ctrl.mpf
.................\.........\init_statemachine.vhd
.................\.........\io_registers.vhd
.................\.........\io_registers2.vhd
.................\.........\ipic_if.vhd
.................\.........\read_data_path2.vhd
.................\.........\read_data_path2a.vhd
.................\.........\read_data_path2_old.vhd

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