Introduction - If you have any usage issues, please Google them yourself
MIL-STD 1 1553B is a centralized control, time-division instruction/response multi-path serial data bus standard
With high reliability and flexibility, it has become the most effective solution for the interconnection of modern airborne airborne systems
The solution is widely used in aircraft, ships, tanks and other weapon platforms, and more and more applications are applied
Civilian areas. The key component of the 1553B bus data transmission function is bus interface chip 11] [41.
After studying the data bus protocol of M STD 1 1553B data bus, the functional junction of some foreign chips is referenced
The design scheme of 1553B bus interface chip based on FPGA is presented in this paper.
After introducing the structure and function of the bus controller BC and the remote terminal RT, a BC based on FPGA is presented.
The specific module design of RT, choose which terminal mode can be configured by working mode. each
The design of the terminal gives a detailed analysis of logical structure, design process and function simulation
After the optimization and synthesis of EDA tools, it was realized on XIL knife heqiao rtex 1 4.
The work is carried out in the test environment of the standard 1553B interface board and the design experiment board
It can be tested to show that this design can work in two modes of BC, and can handle multiple message formats and tools
With strong detection ability, it can cope with the various message formats transmitted on the bus, and the results of verification show that this paper is mentioned in this paper
The design scheme is reasonable.