Several examples of VHDL programming

VHDL
....\实验1
....\.....\part1
....\.....\.....\cmp_state.ini
....\.....\.....\db
....\.....\.....\..\part1.asm.qmsg
....\.....\.....\..\part1.cbx.xml
....\.....\.....\..\part1.cmp.cdb
....\.....\.....\..\part1.cmp.hdb
....\.....\.....\..\part1.cmp.kpt
....\.....\.....\..\part1.cmp.logdb
....\.....\.....\..\part1.cmp.rdb
....\.....\.....\..\part1.cmp.tdb
....\.....\.....\..\part1.cmp0.ddb
....\.....\.....\..\part1.dbp
....\.....\.....\..\part1.db_info
....\.....\.....\..\part1.eco.cdb
....\.....\.....\..\part1.fit.qmsg
....\.....\.....\..\part1.hier_info
....\.....\.....\..\part1.hif
....\.....\.....\..\part1.map.cdb
....\.....\.....\..\part1.map.hdb
....\.....\.....\..\part1.map.logdb
....\.....\.....\..\part1.map.qmsg
....\.....\.....\..\part1.pre_map.cdb
....\.....\.....\..\part1.pre_map.hdb
....\.....\.....\..\part1.psp
....\.....\.....\..\part1.rtlv.hdb
....\.....\.....\..\part1.rtlv_sg.cdb
....\.....\.....\..\part1.rtlv_sg_swap.cdb
....\.....\.....\..\part1.sgdiff.cdb
....\.....\.....\..\part1.sgdiff.hdb
....\.....\.....\..\part1.signalprobe.cdb
....\.....\.....\..\part1.sim.hdb
....\.....\.....\..\part1.sim.qmsg
....\.....\.....\..\part1.sim.rdb
....\.....\.....\..\part1.sim.vwf
....\.....\.....\..\part1.sld_design_entry.sci
....\.....\.....\..\part1.sld_design_entry_dsc.sci
....\.....\.....\..\part1.syn_hier_info
....\.....\.....\..\part1.tan.qmsg
....\.....\.....\..\part1_cmp.qrpt
....\.....\.....\..\wed.zsf
....\.....\.....\DE2.qpf
....\.....\.....\DE2.qws
....\.....\.....\part1.asm.rpt
....\.....\.....\part1.done
....\.....\.....\part1.fit.eqn
....\.....\.....\part1.fit.rpt
....\.....\.....\part1.fit.summary
....\.....\.....\part1.flow.rpt
....\.....\.....\part1.map.eqn
....\.....\.....\part1.map.rpt
....\.....\.....\part1.map.summary
....\.....\.....\part1.pin
....\.....\.....\part1.qsf
....\.....\.....\part1.sim.rpt
....\.....\.....\part1.tan.rpt
....\.....\.....\part1.tan.summary
....\.....\.....\part1.vhd
....\.....\.....\part1.vwf
....\.....\.....\part1_assignment_defaults.qdf
....\.....\part2
....\.....\.....\cmp_state.ini
....\.....\.....\db
....\.....\.....\..\part2.asm.qmsg
....\.....\.....\..\part2.cbx.xml
....\.....\.....\..\part2.cmp.cdb
....\.....\.....\..\part2.cmp.hdb
....\.....\.....\..\part2.cmp.kpt
....\.....\.....\..\part2.cmp.logdb
....\.....\.....\..\part2.cmp.rdb
....\.....\.....\..\part2.cmp.tdb
....\.....\.....\..\part2.cmp0.ddb
....\.....\.....\..\part2.dbp
....\.....\.....\..\part2.db_info
....\.....\.....\..\part2.eco.cdb
....\.....\.....\..\part2.fit.qmsg
....\.....\.....\..\part2.hier_info
....\.....\.....\..\part2.hif
....\.....\.....\..\part2.map.cdb
....\.....\.....\..\part2.map.hdb
....\.....\.....\..\part2.map.logdb
....\.....\.....\..\part2.map.qmsg
....\.....\.....\..\part2.pre_map.cdb
....\.....\.....\..\part2.pre_map.hdb
....\.....\.....\..\part2.psp
....\.....\.....\..\part2.rtlv.hdb
....\.....\.....\..\part2.rtlv_sg.cdb
....\.....\.....\..\part2.rtlv_sg_swap.cdb
....\.....\.....\..\part2.sgdiff.cdb
....\.....\.....\..\part2.sgdiff.hdb
....\.....\.....\..\part2.signalprobe.cdb
....\.....\.....\..\part2.sim.hdb
....\.....\.....\..\part2.sim.qmsg
....\.....\.....\..\part2.sim.rdb
....\.....\.....\..\part2.sim.vwf
....\.....\.....\..\part2.sld_design_entry.sci
....\.....\.....\..\part2.sld_design_entry_dsc.sci
....\.....\.....\..\part2.syn_hier_info

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