In the Altera chip 2C35F672 platform FFT procedures DSPBuilder5.0, generated Verilog file. Development Environment: QuartusII5.0.

FFT
...\fft_example.bsf
...\fft_example.html
...\fft_example.v
...\fft_example.vo
...\fft_example_1n1024cos.hex
...\fft_example_1n1024sin.hex
...\fft_example_2n1024cos.hex
...\fft_example_2n1024sin.hex
...\fft_example_3n1024cos.hex
...\fft_example_3n1024sin.hex
...\fft_example_bb.v
...\fft_example_model.m
...\fft_example_tb.m
...\fft_example_tb.v
...\fft_example_tb.vhd
...\fft_example_vho_msim.tcl
...\fft_example_vo_msim.tcl
...\fft_example_wave.do
...\imag_input.txt
...\real_input.txt

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