based on VHDL write DS18B20 driven, simple version

ds18b20
.......\Block1.bdf
.......\cmp_state.ini
.......\db
.......\..\add_sub_lsh.tdf
.......\..\add_sub_msh.tdf
.......\..\altsyncram_3rj.tdf
.......\..\ds18b20.atom.rvd
.......\..\ds18b20.cbx.xml
.......\..\ds18b20.cmp.rdb
.......\..\ds18b20.dbp
.......\..\ds18b20.db_info
.......\..\ds18b20.eco.cdb
.......\..\ds18b20.hier_info
.......\..\ds18b20.hif
.......\..\ds18b20.map.cdb
.......\..\ds18b20.map.hdb
.......\..\ds18b20.map.logdb
.......\..\ds18b20.map.qmsg
.......\..\ds18b20.pre_map.cdb
.......\..\ds18b20.pre_map.hdb
.......\..\ds18b20.psp
.......\..\ds18b20.pss
.......\..\ds18b20.rpp.qmsg
.......\..\ds18b20.rtlv.hdb
.......\..\ds18b20.rtlv_sg.cdb
.......\..\ds18b20.rtlv_sg_swap.cdb
.......\..\ds18b20.sgate.rvd
.......\..\ds18b20.sgate_sm.rvd
.......\..\ds18b20.sgdiff.cdb
.......\..\ds18b20.sgdiff.hdb
.......\..\ds18b20.sim.vwf
.......\..\ds18b20.sld_design_entry.sci
.......\..\ds18b20.sld_design_entry_dsc.sci
.......\..\ds18b20.sta.qmsg
.......\..\ds18b20.syn_hier_info
.......\..\ds18b200.rtl.mif
.......\..\ds18b20_cmp.qrpt
.......\..\ds18b20_sim.qrpt
.......\..\mux_jcc.tdf
.......\..\wed.wsf
.......\ds18b20.asm.rpt
.......\ds18b20.bsf
.......\ds18b20.cdf
.......\ds18b20.done
.......\ds18b20.dpf
.......\ds18b20.fit.eqn
.......\ds18b20.fit.rpt
.......\ds18b20.fit.summary
.......\ds18b20.flow.rpt
.......\ds18b20.map.eqn
.......\ds18b20.map.rpt
.......\ds18b20.map.summary
.......\ds18b20.pin
.......\ds18b20.pof
.......\ds18b20.qpf
.......\ds18b20.qsf
.......\ds18b20.qws
.......\ds18b20.sdc
.......\ds18b20.sim.rpt
.......\ds18b20.sof
.......\ds18b20.tan.rpt
.......\ds18b20.tan.summary
.......\ds18b20.v
.......\ds18b20.vhd
.......\ds18b20.vwf
.......\ds18b20_assignment_defaults.qdf

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