the procedures to XILINX ISE8.2 for the development platform VHDL used for the development of language, the right to achieve a clock frequency of the signal function

ClockDiv.bld
ClockDiv.cmd_log
ClockDiv.ise
ClockDiv.ise_ISE_Backup
ClockDiv.lso
ClockDiv.ncd
ClockDiv.ngc
ClockDiv.ngd
ClockDiv.ngr
ClockDiv.ntrc_log
ClockDiv.pad
ClockDiv.par
ClockDiv.pcf
ClockDiv.prj
ClockDiv.stx
ClockDiv.syr
ClockDiv.tdo
clockdiv.twr
clockdiv.twx
ClockDiv.udo
ClockDiv.unroutes
ClockDiv.vhd
ClockDiv.xpi
ClockDiv.xst
ClockDiv_last_par.ncd
ClockDiv_map.mrp
ClockDiv_map.ncd
ClockDiv_map.ngm
ClockDiv_pad.csv
ClockDiv_pad.txt
ClockDiv_summary.html
ClockDiv_tbw.ano
ClockDiv_tbw.ant
ClockDiv_tbw.jhd
ClockDiv_tbw.mdo
ClockDiv_tbw.ndo
ClockDiv_tbw.tbw
ClockDiv_tbw.tdo
ClockDiv_tbw.udo
ClockDiv_tbw.vhw
ClockDiv_tbw.xwv
ClockDiv_tbw.xwv_bak
ClockDiv_tbw_beh.prj
ClockDiv_tbw_bencher.prj
ClockDiv_tbw_gen.prj
ClockDiv_tbw_isim_beh.exe
ClockDiv_tbw_isim_par.exe
ClockDiv_tbw_par.prj
ClockDiv_tbw_tbxr.exe
genExpectedResults.cmd
isim
....\simprim_ver.auxlib
....\..................\ffsrce
....\..................\......\ffsrce.h
....\..................\......\mingw
....\..................\......\.....\ffsrce.obj
....\..................\hdllib.ref
....\..................\sffsrce
....\..................\.......\mingw
....\..................\.......\.....\sffsrce.obj
....\..................\.......\sffsrce.h
....\..................\_x___b_u_f
....\..................\..........\mingw
....\..................\..........\.....\_x___b_u_f.obj
....\..................\..........\_x___b_u_f.h
....\..................\_x___c_k_b_u_f
....\..................\..............\mingw
....\..................\..............\.....\_x___c_k_b_u_f.obj
....\..................\..............\_x___c_k_b_u_f.h
....\..................\_x___f_f
....\..................\........\mingw
....\..................\........\.....\_x___f_f.obj
....\..................\........\_x___f_f.h
....\..................\_x___i_n_v
....\..................\..........\mingw
....\..................\..........\.....\_x___i_n_v.obj
....\..................\..........\_x___i_n_v.h
....\..................\_x___i_p_a_d
....\..................\............\mingw
....\..................\............\.....\_x___i_p_a_d.obj
....\..................\............\_x___i_p_a_d.h
....\..................\_x___l_u_t4
....\..................\...........\mingw
....\..................\...........\.....\_x___l_u_t4.obj
....\..................\...........\_x___l_u_t4.h
....\..................\_x___o_b_u_f
....\..................\............\mingw
....\..................\............\.....\_x___o_b_u_f.obj
....\..................\............\_x___o_b_u_f.h
....\..................\_x___o_n_e
....\..................\..........\mingw
....\..................\..........\.....\_x___o_n_e.obj
....\..................\..........\_x___o_n_e.h
....\..................\_x___o_p_a_d
....\..................\............\mingw
....\..................\............\.....\_x___o_p_a_d.obj
....\..................\............\_x___o_p_a_d.h
....\..................\_x___s_f_f
....\..................\..........\mingw
....\..................\..........\.....\_x___s_f_f.obj

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