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interpolation_FIR

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 24kb
  • Downloaded :0次
  • Author :Jack
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
Interpolation FIR Design Example for Stratix Devices
Packet file list
(Preview for download)
impulse.vwf
inter_poly.m
inter_poly.v
mult_add.v
pll.v
random.vwf
rom0.mif
rom0.v
rom1.mif
rom1.v
rom2.mif
rom2.v
rom3.mif
rom3.v
step.vwf
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