FPGA on the verilog language programming. Lookup table through direct digital frequency synthesis. In part through the control of the keyboard to choose sine, square, triangle wave, sloping wave, and four arbitrary waveform two superposed and the stack of four waveform; by controlling the frequency control word on the size, in order to control the output waveform frequency, 1 Hz to achieve the fine-tuning; Address transform through waveform phase adjustable 256; DAC0832 so through waveform amplitude adjustable 256; FPGA through internal RAM to the waveform storage intervals; and achieve a 100 per second sweep 9999.

DDS
...\clock_d2.v
...\control.v
...\datachoose.v
...\DDS.v
...\LPM_SHIFTREa.v
...\LPM_SHIFTREa_bb.v
...\LPM_SHIFTREa_inst.v
...\MUX.v
...\MUX_bb.v
...\MUX_inst.v
...\RAM.v
...\RAM_bb.v
...\RAM_inst.v
...\risewave.v
...\romlookup.v
...\romlookup_bb.v
...\squwave.v
...\triawave.v

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