the verilog code input and output is a classic example. Together reference.

sim
...\comp_altera_lib.do
...\comp_gate.do
...\diff_io_top.vo
...\diff_io_top_v.sdo
...\gate_sim.do
...\stratix
...\.......\@p@r@i@m_@d@f@f@e
...\.......\.................\verilog.asm
...\.......\.................\_primary.dat
...\.......\.................\_primary.vhd
...\.......\and1
...\.......\....\verilog.asm
...\.......\....\_primary.dat
...\.......\....\_primary.vhd
...\.......\and16
...\.......\.....\verilog.asm
...\.......\.....\_primary.dat
...\.......\.....\_primary.vhd
...\.......\b17mux21
...\.......\........\verilog.asm
...\.......\........\_primary.dat
...\.......\........\_primary.vhd
...\.......\b5mux21
...\.......\.......\verilog.asm
...\.......\.......\_primary.dat
...\.......\.......\_primary.vhd
...\.......\bmux21
...\.......\......\verilog.asm
...\.......\......\_primary.dat
...\.......\......\_primary.vhd
...\.......\dffe
...\.......\....\verilog.asm
...\.......\....\_primary.dat
...\.......\....\_primary.vhd
...\.......\latch
...\.......\.....\verilog.asm
...\.......\.....\_primary.dat
...\.......\.....\_primary.vhd
...\.......\mux21
...\.......\.....\verilog.asm
...\.......\.....\_primary.dat
...\.......\.....\_primary.vhd
...\.......\m_cntr
...\.......\......\verilog.asm
...\.......\......\_primary.dat
...\.......\......\_primary.vhd
...\.......\nmux21
...\.......\......\verilog.asm
...\.......\......\_primary.dat
...\.......\......\_primary.vhd
...\.......\n_cntr
...\.......\......\verilog.asm
...\.......\......\_primary.dat
...\.......\......\_primary.vhd
...\.......\scale_cntr
...\.......\..........\verilog.asm
...\.......\..........\_primary.dat
...\.......\..........\_primary.vhd
...\.......\stratix_asynch_io
...\.......\.................\verilog.asm
...\.......\.................\_primary.dat
...\.......\.................\_primary.vhd
...\.......\stratix_asynch_lcell
...\.......\....................\verilog.asm
...\.......\....................\_primary.dat
...\.......\....................\_primary.vhd
...\.......\stratix_crcblock
...\.......\................\verilog.asm
...\.......\................\_primary.dat
...\.......\................\_primary.vhd
...\.......\stratix_io
...\.......\..........\verilog.asm
...\.......\..........\_primary.dat
...\.......\..........\_primary.vhd
...\.......\stratix_io_register
...\.......\...................\verilog.asm
...\.......\...................\_primary.dat
...\.......\...................\_primary.vhd
...\.......\stratix_jtag
...\.......\............\verilog.asm
...\.......\............\_primary.dat
...\.......\............\_primary.vhd
...\.......\stratix_lcell
...\.......\.............\verilog.asm
...\.......\.............\_primary.dat
...\.......\.............\_primary.vhd
...\.......\stratix_lcell_register
...\.......\......................\verilog.asm
...\.......\......................\_primary.dat
...\.......\......................\_primary.vhd
...\.......\stratix_lvds_receiver
...\.......\.....................\verilog.asm
...\.......\.....................\_primary.dat
...\.......\.....................\_primary.vhd
...\.......\stratix_lvds_rx_parallel_register
...\.......\.................................\verilog.asm
...\.......\.................................\_primary.dat
...\.......\.................................\_primary.vhd
...\.......\stratix_lvds_transmitter

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