Orangk'aes algorithm verilog hdl realized, we supply as a reference.

mini_aes
........\mini_aes
........\........\bench
........\........\.....\input.vhdl
........\........\.....\modelsim_bench.do
........\........\.....\modelsim_bench.vhdl
........\........\.....\output.vhdl
........\........\data
........\........\....\ecb_tbl.txt
........\........\....\xilinx_fpga.ucf
........\........\doc
........\........\...\acrobat_view
........\........\...\aes128block.eps
........\........\...\area.eps
........\........\...\circuit_schematic.eps
........\........\...\key_scheduler.eps
........\........\...\Makefile
........\........\...\mini_aes.pdf
........\........\...\mini_aes.tex
........\........\...\oc_logo.eps
........\........\README
........\........\source
........\........\......\bram_block_a.vhdl
........\........\......\bram_block_b.vhdl
........\........\......\counter2bit.vhdl
........\........\......\folded_register.vhdl
........\........\......\io_interface.vhdl
........\........\......\key_scheduler.vhdl
........\........\......\mini_aes.vhdl
........\........\......\mix_column.vhdl
........\........\......\xtime.vhdl

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