using FPGA full-duplex asynchronous serial port (UART), and PC communication. An initiation; 8 data spaces; One-stop; No Parity; Baud Rate for 2400,4800,9600, 11520 optional or variable (baud rate can be used to control keypad mode).

vhdl
....\example
....\.......\Chapter5 Sample
....\.......\...............\UART
....\.......\...............\....\automake.log
....\.......\...............\....\baudrate_generator.jhd
....\.......\...............\....\baudrate_generator.vhd
....\.......\...............\....\baudrate_generator_TB.jhd
....\.......\...............\....\baudrate_generator_TB.vhd
....\.......\...............\....\counter.jhd
....\.......\...............\....\counter.vhd
....\.......\...............\....\counter_TB.jhd
....\.......\...............\....\counter_TB.vhd
....\.......\...............\....\detector.jhd
....\.......\...............\....\detector.vhd
....\.......\...............\....\detector_TB.jhd
....\.......\...............\....\detector_TB.vhd
....\.......\...............\....\parity_verifier.jhd
....\.......\...............\....\parity_verifier.vhd
....\.......\...............\....\parity_verifier_TB.jhd
....\.......\...............\....\parity_verifier_TB.vhd
....\.......\...............\....\shift_register.jhd
....\.......\...............\....\shift_register.vhd
....\.......\...............\....\shift_register_TB.jhd
....\.......\...............\....\shift_register_TB.vhd
....\.......\...............\....\switch.jhd
....\.......\...............\....\switch.vhd
....\.......\...............\....\switch_bus.jhd
....\.......\...............\....\switch_bus.vhd
....\.......\...............\....\switch_bus_TB.jhd
....\.......\...............\....\switch_bus_TB.vhd
....\.......\...............\....\UART.npl
....\.......\...............\....\uart_core.jhd
....\.......\...............\....\uart_core.vhd
....\.......\...............\....\UART_PACKAGE.vhd
....\.......\...............\....\uart_top.jhd
....\.......\...............\....\uart_top.vhd
....\.......\...............\....\uart_top_tb.jhd
....\.......\...............\....\uart_top_tb.vhd
....\.......\...............\....\__projnav
....\.......\...............\....\.........\p00p5000.kis
....\.......\...............\....\.........\p00pi000.kis
....\.......\...............\....\.........\p00pl000.kis
....\.......\...............\....\.........\runXst_tcl.rsp
....\.......\...............\....\__projnav.log

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