prepared using Verilog HDL, a 50% duty cycle for the six sub-frequency circuit

mod6_divide
...........\db
...........\..\mod6_divide.asm.qmsg
...........\..\mod6_divide.cbx.xml
...........\..\mod6_divide.cmp.cdb
...........\..\mod6_divide.cmp.hdb
...........\..\mod6_divide.cmp.kpt
...........\..\mod6_divide.cmp.logdb
...........\..\mod6_divide.cmp.rdb
...........\..\mod6_divide.cmp.tdb
...........\..\mod6_divide.cmp0.ddb
...........\..\mod6_divide.dbp
...........\..\mod6_divide.db_info
...........\..\mod6_divide.eco.cdb
...........\..\mod6_divide.fit.qmsg
...........\..\mod6_divide.hier_info
...........\..\mod6_divide.hif
...........\..\mod6_divide.map.cdb
...........\..\mod6_divide.map.hdb
...........\..\mod6_divide.map.logdb
...........\..\mod6_divide.map.qmsg
...........\..\mod6_divide.pre_map.cdb
...........\..\mod6_divide.pre_map.hdb
...........\..\mod6_divide.psp
...........\..\mod6_divide.rtlv.hdb
...........\..\mod6_divide.rtlv_sg.cdb
...........\..\mod6_divide.rtlv_sg_swap.cdb
...........\..\mod6_divide.sgdiff.cdb
...........\..\mod6_divide.sgdiff.hdb
...........\..\mod6_divide.signalprobe.cdb
...........\..\mod6_divide.sld_design_entry.sci
...........\..\mod6_divide.sld_design_entry_dsc.sci
...........\..\mod6_divide.syn_hier_info
...........\..\mod6_divide.tan.qmsg
...........\mod6_divide.asm.rpt
...........\mod6_divide.bsf
...........\mod6_divide.done
...........\mod6_divide.fit.rpt
...........\mod6_divide.fit.smsg
...........\mod6_divide.fit.summary
...........\mod6_divide.flow.rpt
...........\mod6_divide.map.rpt
...........\mod6_divide.map.summary
...........\mod6_divide.pin
...........\mod6_divide.pof
...........\mod6_divide.qpf
...........\mod6_divide.qsf
...........\mod6_divide.sof
...........\mod6_divide.tan.rpt
...........\mod6_divide.tan.summary
...........\mod6_divide.v

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