This is the language I used vhdl in fpga done an internal dual-port ram procedures. My mail : wleechina@163.com

dpram2
......\.untf
......\bitgen.ut
......\coregen.prj
......\dpram2.bgn
......\dpram2.bit
......\dpram2.bld
......\dpram2.cmd_log
......\dpram2.dhp
......\dpram2.drc
......\dpram2.lso
......\dpram2.mrp
......\dpram2.nc1
......\dpram2.ncd
......\dpram2.ngc
......\dpram2.ngd
......\dpram2.ngm
......\dpram2.ngr
......\dpram2.npl
......\dpram2.pad
......\dpram2.pad_txt
......\dpram2.par
......\dpram2.pcf
......\dpram2.placed_ncd_tracker
......\dpram2.prj
......\dpram2.routed_ncd_tracker
......\dpram2.stx
......\dpram2.syr
......\dpram2.twr
......\dpram2.twx
......\dpram2.ut
......\dpram2.vhd
......\dpram2.xpi
......\dpram2_map.ncd
......\dpram2_map.ngm
......\dpram2_pad.csv
......\dpram2_pad.txt
......\dpram2_vhdl.prj
......\pepExtractor.prj
......\results.txt
......\test.ANT
......\test.fdo
......\test.tbw
......\test.udo
......\test.vhw
......\transcript
......\vsim.wlf
......\work
......\....\dpram2
......\....\......\behavioral.dat
......\....\......\behavioral.psm
......\....\......\_primary.dat
......\....\dpram2_cfg
......\....\..........\_primary.dat
......\....\..........\_vhdl.psm
......\....\test
......\....\....\testbench_arch.dat
......\....\....\testbench_arch.psm
......\....\....\_primary.dat
......\....\_info
......\xst
......\...\work
......\...\....\hdllib.ref
......\...\....\hdpdeps.ref
......\...\....\sub00
......\...\....\.....\vhpl00.vho
......\...\....\.....\vhpl01.vho
......\_ngo
......\....\netlist.lst
......\__projnav
......\.........\bitgen.rsp
......\.........\coregen.rsp
......\.........\dpram2.gfl
......\.........\dpram2.xst
......\.........\dpram2_flowplus.gfl
......\.........\dpram2_ncdTOut_tcl.rsp
......\.........\ednTOngd_tcl.rsp
......\.........\hb_cmds
......\.........\nc1TOncd_tcl.rsp
......\.........\runXst_tcl.rsp
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