complete with verilog language development USB2.0 IP source code, including documentation, Simulation documents

USB2.0的IP核，包含文档和Verilog源码
...................................\usb_funct
...................................\.........\bench
...................................\.........\.....\CVS
...................................\.........\.....\...\Entries
...................................\.........\.....\...\Repository
...................................\.........\.....\...\Root
...................................\.........\.....\verilog
...................................\.........\.....\.......\CVS
...................................\.........\.....\.......\...\Entries
...................................\.........\.....\.......\...\Repository
...................................\.........\.....\.......\...\Root
...................................\.........\doc
...................................\.........\...\CVS
...................................\.........\...\...\Entries
...................................\.........\...\...\Repository
...................................\.........\...\...\Root
...................................\.........\...\README.txt
...................................\.........\...\STATUS.txt
...................................\.........\...\usb_doc.pdf
...................................\.........\rtl
...................................\.........\...\CVS
...................................\.........\...\...\Entries
...................................\.........\...\...\Repository
...................................\.........\...\...\Root
...................................\.........\...\verilog
...................................\.........\...\.......\CVS
...................................\.........\...\.......\...\Entries
...................................\.........\...\.......\...\Repository
...................................\.........\...\.......\...\Root
...................................\.........\...\.......\usbf_crc16.v
...................................\.........\...\.......\usbf_crc5.v
...................................\.........\...\.......\usbf_defines.v
...................................\.........\...\.......\usbf_ep_rf.v
...................................\.........\...\.......\usbf_ep_rf_dummy.v
...................................\.........\...\.......\usbf_idma.v
...................................\.........\...\.......\usbf_mem_arb.v
...................................\.........\...\.......\usbf_pa.v
...................................\.........\...\.......\usbf_pd.v
...................................\.........\...\.......\usbf_pe.v
...................................\.........\...\.......\usbf_pl.v
...................................\.........\...\.......\usbf_rf.v
...................................\.........\...\.......\usbf_top.v
...................................\.........\...\.......\usbf_utmi_if.v
...................................\.........\...\.......\usbf_utmi_ls.v
...................................\.........\...\.......\usbf_wb.v
...................................\.........\sim
...................................\.........\...\CVS
...................................\.........\...\...\Entries
...................................\.........\...\...\Repository
...................................\.........\...\...\Root
...................................\.........\...\rtl_sim
...................................\.........\...\.......\bin
...................................\.........\...\.......\...\CVS
...................................\.........\...\.......\...\...\Entries
...................................\.........\...\.......\...\...\Repository
...................................\.........\...\.......\...\...\Root
...................................\.........\...\.......\CVS
...................................\.........\...\.......\...\Entries
...................................\.........\...\.......\...\Repository
...................................\.........\...\.......\...\Root
...................................\.........\...\.......\run
...................................\.........\...\.......\...\CVS
...................................\.........\...\....

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