with an FPGA 16FFT, not only as a reference document projects

do
..\compile_all.do
..\compile_tb_fio.do
..\comp_sim_run_fio.do
fft16xk.dat
modelsim.ini
r4difv1.exe
readme_beh_VHDL.doc
tb_xfft16_fio.vhd
vhdl
....\bflywj.vhd
....\bitrev_agen.vhd
....\bitrev_dbufr.vhd
....\blyw0.vhd
....\cb2re.vhd
....\cb8re.vhd
....\cmplxadd.vhd
....\cmplxsub16.vhd
....\cmplx_mul16.vhd
....\coss16.vhd
....\dblbufr.vhd
....\dblbufr1.vhd
....\dfly_agen.vhd
....\dual_xlatch16.vhd
....\fd.vhd
....\fdc.vhd
....\fdre.vhd
....\fdre_locx.vhd
....\fdre_locy.vhd
....\fft16.vhd
....\fft256r4.vhd
....\fft4.vhd
....\fft4r.vhd
....\ftrse.vhd
....\mathpack.vhd
....\mulxx.vhd
....\mux21w16.vhd
....\mux2w4.vhd
....\mux2w4r.vhd
....\mux4w16.vhd
....\mux4w8.vhd
....\phases.vhd
....\r4butterfly.vhd
....\r4n256w.vhd
....\radd16.vhd
....\ramd1616.vhd
....\reg16.vhd
....\reg16_pitch2.vhd
....\reg4.vhd
....\reg8.vhd
....\result.vhd
....\rmux4w16.vhd
....\rsub16.vhd
....\sinn16.vhd
....\state_control.vhd
....\tcompw16.vhd
....\triginv.vhd
....\xfft1024_cntrl.vhd
....\xfft16.vhd
....\z17w8.vhd
....\z4_1.vhd
....\z4_1_h.vhd
....\z5w16.vhd
xfft_cmpr.m
xin.dat
xk_cmpr.m
xnoisesig.m

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