agreement on the serial port, with vlog prepared. The development environment is modulesim!

spi
...\signal_send_and_recerv.v
...\spi.cr.mti
...\spi.do.wlf
...\spi.mpf
...\spi_miso_in.do.wlf
...\spi_mosi_out.do.wlf
...\spi_tb.v
...\vsim.wlf
...\work
...\....\spi_tb
...\....\......\verilog.asm
...\....\......\_primary.dat
...\....\......\_primary.vhd
...\....\spi_top
...\....\.......\verilog.asm
...\....\.......\_primary.dat
...\....\.......\_primary.vhd
...\....\_info

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