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vhdl源程序

  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2012-11-26
  • Size : 4kb
  • Downloaded :0次
  • Author :刘杰
  • About : Nobody
  • PS : If download it fails, try it again. Download again for free!
Introduction - If you have any usage issues, please Google them yourself
some vhdl design example .with WHEN ELSE sentence
Packet file list
(Preview for download)
FIFO.txt
元件例化与层次设计.txt
加法器:generate语句的应用.txt
条件赋值:使用when else语句.vhd
条件赋值:使用列举类型.vhd
条件赋值:使用多路选择器.vhd
计数器:generate语句的应用.txt
计数器:std_logic_unsigned的用法.txt
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