digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), the digital technology in the field of communications is widely used, the cases described in VHDL as a PLL reference source has been tuned. Compiler synplicty.Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the data locked up and the descending; Top-level document is PLL.GDF

pll
...\aa.gdf
...\edge.acf
...\edge.fit
...\edge.gdf
...\edge.hex
...\edge.hif
...\edge.mmf
...\edge.ndb
...\edge.pin
...\edge.pof
...\edge.rpt
...\edge.scf
...\edge.snf
...\edge.sof
...\edge.ttf
...\inst1.gdf
...\mealy1.acf
...\mealy1.fit
...\mealy1.gdf
...\mealy1.hex
...\mealy1.hif
...\mealy1.mmf
...\mealy1.ndb
...\mealy1.pin
...\mealy1.pof
...\mealy1.rpt
...\mealy1.scf
...\mealy1.snf
...\mealy1.sof
...\mealy1.ttf
...\pll.acf
...\pll.fit
...\pll.gdf
...\pll.hif
...\pll.jam
...\pll.jbc
...\pll.mmf
...\pll.ndb
...\pll.pin
...\pll.pof
...\pll.rpt
...\pll.scf
...\pll.snf
...\pll1.acf
...\pll1.fit
...\pll1.gdf
...\pll1.hif
...\pll1.jam
...\pll1.jbc
...\pll1.mmf
...\pll1.ndb
...\pll1.pin
...\pll1.pof
...\pll1.rpt
...\pll1.snf
read me.txt

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