made a ModelSim simulation based on the Verilog source code

covlen
......\convlen_test.v
......\convl_en.v
......\dff.v
covlen2
.......\ConEncdJprj.cr.mti
.......\ConEncdJprj.mpf
.......\ConvEncdJA.bak
.......\ConvEncdJA.v
.......\ConvEncdTestBnch.v
.......\vsim.wlf
.......\work
.......\....\@conv@encd@test@bnch
.......\....\....................\verilog.asm
.......\....\....................\_primary.dat
.......\....\....................\_primary.vhd
.......\....\conv_encode
.......\....\...........\verilog.asm
.......\....\...........\_primary.dat
.......\....\...........\_primary.vhd
.......\....\ser2par
.......\....\.......\verilog.asm
.......\....\.......\_primary.dat
.......\....\.......\_primary.vhd
.......\....\top_encode
.......\....\..........\verilog.asm
.......\....\..........\_primary.dat
.......\....\..........\_primary.vhd
.......\....\_info
covlen3
.......\ASIC_Book_Encoder.cr.mti
.......\ASIC_Book_Encoder.mpf
.......\convl3_en.v
.......\convlen3_test.v
.......\dff.v
.......\vsim.wlf
.......\work
.......\....\convl3_en
.......\....\.........\verilog.asm
.......\....\.........\_primary.dat
.......\....\.........\_primary.vhd
.......\....\convlen3_test
.......\....\.............\verilog.asm
.......\....\.............\_primary.dat
.......\....\.............\_primary.vhd
.......\....\dff
.......\....\...\verilog.asm
.......\....\...\_primary.dat
.......\....\...\_primary.vhd
.......\....\_info
HDL_exmple
..........\EX1_MUX
..........\.......\muxstr.v
..........\.......\testformuxstr.v
..........\EX2_CNT
..........\.......\COUNTER.V
..........\.......\TCOUNTER.V
..........\EX3_ADD
..........\.......\ADDER.VHD
..........\.......\testadder.vhd
..........\EX4_VHDL
..........\........\QUEUE.VHD
..........\........\tb_traffic.vhd
..........\........\TRAFFIC.VHD
keyscan
.......\keyscan
.......\keyscan.v
.......\keyscanprj.cr.mti
.......\keyscanprj.mpf
.......\keyscan_test.v
.......\modelsim.tcl
.......\vsim.wlf
.......\work
.......\....\keyscan
.......\....\.......\fast.dt2
.......\....\.......\verilog.asm
.......\....\.......\_primary.dat
.......\....\.......\_primary.vhd
.......\....\keyscan_test
.......\....\............\fast.asm
.......\....\............\fast.dt2
.......\....\............\verilog.asm
.......\....\............\_primary.dat
.......\....\............\_primary.vhd
.......\....\_info

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