51 VERILOG code! In Xilinx FPGA

oc8051
......\.nclaunch.dd
......\asm
......\...\cast.c
......\...\counter_test.asm
......\...\CVS
......\...\...\Entries
......\...\...\Repository
......\...\...\Root
......\...\DIV16U.asm
......\...\divmul.c
......\...\fib.c
......\...\gcd.c
......\...\hex
......\...\...\cast.hex
......\...\...\counter_test.hex
......\...\...\CVS
......\...\...\...\Entries
......\...\...\...\Repository
......\...\...\...\Root
......\...\...\div16u.hex
......\...\...\divmul.hex
......\...\...\fib.hex
......\...\...\gcd.hex
......\...\...\int2bin.hex
......\...\...\interrupt_test.hex
......\...\...\lcall.hex
......\...\...\negcnt.hex
......\...\...\r_bank.hex
......\...\...\serial_test.hex
......\...\...\sort.hex
......\...\...\sqroot.hex
......\...\...\testall.hex
......\...\...\timer_test.hex
......\...\...\xram.hex
......\...\...\xram_m.ihx
......\...\in
......\...\..\cast.in
......\...\..\counter_test.in
......\...\..\CVS
......\...\..\...\Entries
......\...\..\...\Repository
......\...\..\...\Root
......\...\..\div16u.in
......\...\..\divmul.in
......\...\..\fib.in
......\...\..\gcd.in
......\...\..\int2bin.in
......\...\..\interrupt_test.in
......\...\..\lcall.in
......\...\..\negcnt.in
......\...\..\oc8051_xrom.in
......\...\..\r_bank.in
......\...\..\serial_test.in
......\...\..\sort.in
......\...\..\sqroot.in
......\...\..\testall.in
......\...\..\test_xram.in
......\...\..\timer2_test.in
......\...\..\timer_test.in
......\...\..\xram.in
......\...\..\xram_m.in
......\...\..\xrom_test.in
......\...\int2bin.c
......\...\interrupt_test.asm
......\...\lcall.asm
......\...\negcnt.c
......\...\r_bank.asm
......\...\serial_test.asm
......\...\sort.c
......\...\sqroot.c
......\...\test.asm
......\...\testall.asm
......\...\testall.c
......\...\timer2_test.asm
......\...\timer_test.asm
......\...\v
......\...\.\cast.v
......\...\.\counter_test.v
......\...\.\CVS
......\...\.\...\Entries
......\...\.\...\Repository
......\...\.\...\Root
......\...\.\div16u.v
......\...\.\divmul.v
......\...\.\fib.v
......\...\.\gcd.v
......\...\.\int2bin.v
......\...\.\interrupt_test.v
......\...\.\lcall.v
......\...\.\negcnt.v
......\...\.\r_bank.v
......\...\.\serial_test.v
......\...\.\sort.v
......\...\.\sqroot.v
......\...\.\testall.v
......\...\.\timer_test.v
......\...\.\xram.v
......\...\.\xram_m.v
......\...\vec

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