Packet : DDR（双速率）SDRAM控制器参考设计VHDL代码.zip filelist
doc/
doc/ddr_sdram.pdf
model/
model/mt46v4m16.vhd
model/mti_pkg.vhd
route/
route/ddr_sdram.csf
route/ddr_sdram.esf
route/ddr_sdram.quartus
route/ddr_sdram.vqm
route/pll1.vhd
simulation/
simulation/APEX20KE_MF.VHD
simulation/ddr_command.vhd
simulation/ddr_control_interface.vhd
simulation/ddr_data_path.vhd
simulation/ddr_sdram.vhd
simulation/ddr_sdram_tb.vhd
simulation/io_utils.vhd
simulation/lpm_pack.vhd
simulation/modelsim.ini
simulation/mt46v4m16.vhd
simulation/mti_pkg.bak
simulation/mti_pkg.vhd
simulation/pll1.vhd
simulation/readme.txt
simulation/stdlogar.vhd
simulation/util1164.vhd
simulation/wave.do
simulation/work/
simulation/work/altcam/
simulation/work/altcam/behave.dat
simulation/work/altcam/behave.psm
simulation/work/altcam/_primary.dat
simulation/work/altclklock/
simulation/work/altclklock/behavior.dat
simulation/work/altclklock/behavior.psm
simulation/work/altclklock/_primary.dat
simulation/work/altlvds_rx/
simulation/work/altlvds_rx/behavior.dat
simulation/work/altlvds_rx/behavior.psm
simulation/work/altlvds_rx/_primary.dat
simulation/work/altlvds_tx/
simulation/work/altlvds_tx/behavior.dat
simulation/work/altlvds_tx/behavior.psm
simulation/work/altlvds_tx/_primary.dat
simulation/work/command/
simulation/work/command/rtl.dat
simulation/work/command/rtl.psm
simulation/work/command/_primary.dat
simulation/work/control_interface/
simulation/work/control_interface/rtl.dat
simulation/work/control_interface/rtl.psm
simulation/work/control_interface/_primary.dat
simulation/work/ddr_command/
simulation/work/ddr_command/rtl.dat
simulation/work/ddr_command/rtl.psm
simulation/work/ddr_command/_primary.dat
simulation/work/ddr_control_interface/
simulation/work/ddr_control_interface/rtl.dat
simulation/work/ddr_control_interface/rtl.psm
simulation/work/ddr_control_interface/_primary.dat
simulation/work/ddr_data_path/
simulation/work/ddr_data_path/rtl.dat
simulation/work/ddr_data_path/rtl.psm
simulation/work/ddr_data_path/_primary.dat
simulation/work/ddr_sdram/
simulation/work/ddr_sdram/rtl.dat
simulation/work/ddr_sdram/rtl.psm
simulation/work/ddr_sdram/_primary.dat
simulation/work/ddr_sdram_tb/
simulation/work/ddr_sdram_tb/rtl.dat
simulation/work/ddr_sdram_tb/rtl.psm
simulation/work/ddr_sdram_tb/_primary.dat
simulation/work/io_utils/
simulation/work/io_utils/body.dat
simulation/work/io_utils/body.psm
simulation/work/io_utils/_primary.dat
simulation/work/io_utils/_vhdl.psm
simulation/work/lpm_components/
simulation/work/lpm_components/body.dat
simulation/work/lpm_components/body.psm
simulation/work/lpm_components/_primary.dat
simulation/work/lpm_components/_vhdl.psm
simulation/work/mt46v4m16/
simulation/work/mt46v4m16/behave.dat
simulation/work/mt46v4m16/behave.psm
simulation/work/mt46v4m16/_primary.dat
simulation/work/mti_pkg/
simulation/work/mti_pkg/body.dat
simulation/work/mti_pkg/body.psm
simulation/work/mti_pkg/_primary.dat
simulation/work/mti_pkg/_vhdl.psm
simulation/work/pll1/
simulation/work/pll1/syn.dat
simulation/work/pll1/syn.psm
simulation/work/pll1/_primary.dat
simulation/work/std_logic_arith/
simulation/work/std_logic_arith/body.dat
simulation/work/std_logic_arith/body.psm
simulation/work/std_logic_arith/_primary.dat
simulation/work/std_logic_arith/_vhdl.psm
simulation/work/util_1164/
simulation/work/util_1164/body.dat
simulation/work/util_1164/body.psm
simulation/work/util_1164/_primary.dat
simulation/work/util_1164/_vhdl.psm
simulation/work/_info
source/
source/ddr_command.vhd
source/ddr_control_interface.vhd
source/ddr_data_path.vhd
source/ddr_sdram.vhd
synthesis/
synthesis/synplicity/
synthesis/synplicity/ddr_sdram.prj
synthesis/synplicity/rev_1/
synthesis/synplicity/rev_1/ddr_sdram.srm
synthesis/synplicity/rev_1/ddr_sdram.srr
synthesis/synplicity/rev_1/ddr_sdram.srs
synthesis/synplicity/rev_1/ddr_sdram.tcl
synthesis/synplicity/rev_1/ddr_sdram.tlg
synthesis/synplicity/rev_1/ddr_sdram.vqm
synthesis/synplicity/rev_1/ddr_sdram.xrf
synthesis/synplicity/rev_1/ddr_sdram_cons.tcl
synthesis/synplicity/rev_1/ddr_sdram_rm.tcl
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