异步FIFO常用于存储、缓冲在两个异步时钟之间的数据传输。在异步电路中，由于时钟之间周期和相位完全独立，因而数据的丢失概率不为零。如何设计一个高可靠性、高速的异步FIFO电路便成为一个难点。本例采用格雷码方式，用verilog语言实现了异

Packet : FIFO_gray.rar filelist
FIFO_gray\fifo_gray.v
FIFO_gray\ram_gray.v
FIFO_gray\ram_gray_bb.v
FIFO_gray

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