Use Quartus II to design FPGA application design examples "\ Example-b3-1\uart_regs\ SRC" directory is the design source file "\ Example-b3-1\uart_regs\ core" is the IP macro function module of Altera The "\ Example-b3-1\uart_regs\sim\ funcsim" directory is the function simulation file The "\ Example-b3-1\uart_regs\sim\ parsim" directory is the sequence simulation file Under the directory of "\ Example-b3-1\uart_regs\ dev", the project files (including the process files and result files of the constraint, synthesis, layout wiring)

Packet : 15883831example-b3-1.rar filelist
uart_regs\core\myfifo_10.v
uart_regs\core\myfifo_10_bb.v
uart_regs\core\myfifo_10_wave0.jpg
uart_regs\core\myfifo_10_waveforms.html
uart_regs\core\myfifo_8.v
uart_regs\core\myfifo_8_bb.v
uart_regs\core\myfifo_8_wave0.jpg
uart_regs\core\myfifo_8_waveforms.html
uart_regs\dev\chip_editor.acv
uart_regs\dev\cmp_state.ini
uart_regs\dev\db\add_sub_1jh.tdf
uart_regs\dev\db\add_sub_dhh.tdf
uart_regs\dev\db\add_sub_ehh.tdf
uart_regs\dev\db\add_sub_fhh.tdf
uart_regs\dev\db\add_sub_ihh.tdf
uart_regs\dev\db\add_sub_rih.tdf
uart_regs\dev\db\altsyncram_apb1.tdf
uart_regs\dev\db\altsyncram_mmb1.tdf
uart_regs\dev\db\a_dpfifo_4nl.tdf
uart_regs\dev\db\a_dpfifo_rll.tdf
uart_regs\dev\db\a_fefifo_qve.tdf
uart_regs\dev\db\dpram_81k.tdf
uart_regs\dev\db\dpram_h2k.tdf
uart_regs\dev\db\scfifo_eaq.tdf
uart_regs\dev\db\scfifo_nbq.tdf
uart_regs\dev\db\uart_regs(0).cnf.cdb
uart_regs\dev\db\uart_regs(0).cnf.hdb
uart_regs\dev\db\uart_regs(1).cnf.cdb
uart_regs\dev\db\uart_regs(1).cnf.hdb
uart_regs\dev\db\uart_regs(10).cnf.cdb
uart_regs\dev\db\uart_regs(10).cnf.hdb
uart_regs\dev\db\uart_regs(11).cnf.cdb
uart_regs\dev\db\uart_regs(11).cnf.hdb
uart_regs\dev\db\uart_regs(12).cnf.cdb
uart_regs\dev\db\uart_regs(12).cnf.hdb
uart_regs\dev\db\uart_regs(13).cnf.cdb
uart_regs\dev\db\uart_regs(13).cnf.hdb
uart_regs\dev\db\uart_regs(14).cnf.cdb
uart_regs\dev\db\uart_regs(14).cnf.hdb
uart_regs\dev\db\uart_regs(15).cnf.cdb
uart_regs\dev\db\uart_regs(15).cnf.hdb
uart_regs\dev\db\uart_regs(16).cnf.cdb
uart_regs\dev\db\uart_regs(16).cnf.hdb
uart_regs\dev\db\uart_regs(17).cnf.cdb
uart_regs\dev\db\uart_regs(17).cnf.hdb
uart_regs\dev\db\uart_regs(18).cnf.cdb
uart_regs\dev\db\uart_regs(18).cnf.hdb
uart_regs\dev\db\uart_regs(19).cnf.cdb
uart_regs\dev\db\uart_regs(19).cnf.hdb
uart_regs\dev\db\uart_regs(2).cnf.cdb
uart_regs\dev\db\uart_regs(2).cnf.hdb
uart_regs\dev\db\uart_regs(20).cnf.cdb
uart_regs\dev\db\uart_regs(20).cnf.hdb
uart_regs\dev\db\uart_regs(21).cnf.cdb
uart_regs\dev\db\uart_regs(21).cnf.hdb
uart_regs\dev\db\uart_regs(3).cnf.cdb
uart_regs\dev\db\uart_regs(3).cnf.hdb
uart_regs\dev\db\uart_regs(4).cnf.cdb
uart_regs\dev\db\uart_regs(4).cnf.hdb
uart_regs\dev\db\uart_regs(5).cnf.cdb
uart_regs\dev\db\uart_regs(5).cnf.hdb
uart_regs\dev\db\uart_regs(6).cnf.cdb
uart_regs\dev\db\uart_regs(6).cnf.hdb
uart_regs\dev\db\uart_regs(7).cnf.cdb
uart_regs\dev\db\uart_regs(7).cnf.hdb
uart_regs\dev\db\uart_regs(8).cnf.cdb
uart_regs\dev\db\uart_regs(8).cnf.hdb
uart_regs\dev\db\uart_regs(9).cnf.cdb
uart_regs\dev\db\uart_regs(9).cnf.hdb
uart_regs\dev\db\uart_regs-sim.vwf
uart_regs\dev\db\uart_regs.db_info
uart_regs\dev\db\uart_regs_cmp.qrpt
uart_regs\dev\db\uart_regs_hier_info
uart_regs\dev\db\uart_regs_sim.qrpt
uart_regs\dev\db\uart_regs_syn_hier_info
uart_regs\dev\sim.cfg
uart_regs\dev\uart_regs.asm.rpt
uart_regs\dev\uart_regs.done
uart_regs\dev\uart_regs.fit.eqn
uart_regs\dev\uart_regs.fit.rpt
uart_regs\dev\uart_regs.fld
uart_regs\dev\uart_regs.flow.rpt
uart_regs\dev\uart_regs.map.eqn
uart_regs\dev\uart_regs.map.rpt
uart_regs\dev\uart_regs.pin
uart_regs\dev\uart_regs.pof
uart_regs\dev\uart_regs.qpf
uart_regs\dev\uart_regs.qsf
uart_regs\dev\uart_regs.qws
uart_regs\dev\uart_regs.rbf
uart_regs\dev\uart_regs.sim.rpt
uart_regs\dev\uart_regs.sof
uart_regs\dev\uart_regs.tan.rpt
uart_regs\dev\uart_regs.tan.summary
uart_regs\dev\uart_regs_assignment_defaults.qdf
uart_regs\sim\funcsim\uart_regs_h.vwf
uart_regs\sim\funcsim\uart_regs_pre.vwf
uart_regs\src\sch\lpm_mux0.bsf
uart_regs\src\sch\lpm_mux0.v
uart_regs\src\sch\lpm_mux0_bb.v
uart_regs\src\sch\sch_exam.bdf
uart_regs\src\seriesPort.v
uart_regs\src\uart_defines.v
uart_regs\src\uart_receiver.v
uart_regs\src\uart_regs.v
uart_regs\src\uart_transmitter.v
示例说明.doc
uart_regs\src\sch\db
uart_regs\core\db
uart_regs\dev\db
uart_regs\sim\funcsim
uart_regs\sim\parsim
uart_regs\src\sch
uart_regs\core
uart_regs\dev
uart_regs\sim
uart_regs\src
uart_regs

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