Hot Search : Source embeded web remote control p2p game More...
Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog

FP_adder

FavoriteReport
  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2018-04-21
  • Size : 11kb
  • Downloaded ：0次
  • Author ：liki20
  • About ： Nobody
  • PS : If download it fails, try it again. Download again for free!
Download1 Download2
Introduction - If you have any usage issues, please Google them yourself
32 bit floating point adder with testbench
Packet file list
(Preview for download)
FilenameSizeUpdate
FP_adder\.gitignore 35 2017-12-10
FP_adder\adder.v 6920 2017-12-10
FP_adder\c_test\test 8496 2017-12-10
FP_adder\c_test\test.cpp 237 2017-12-10
FP_adder\file_reader_a.v 7932 2017-12-10
FP_adder\file_reader_b.v 7932 2017-12-10
FP_adder\file_writer.v 6825 2017-12-10
FP_adder\run_test.py 6148 2017-12-10
FP_adder\stim_z 0 2017-12-10
FP_adder\test_bench.v 1219 2017-12-10
FP_adder\test_bench_tb.v 316 2017-12-10
FP_adder\c_test 0 2017-12-10
FP_adder 0 2017-12-10
Related instructions
  • We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
  • The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
  • Please use Winrar for decompression tools
  • If download fail, Try it againg or Feedback to us.
  • If downloaded content did not match the introduction, Feedback to us，Confirm and will be refund.
  • Before downloading, you can inquire through the uploaded person information
Comment

Nothing．

Post Comment
*Quick comment Recommend Not bad Password Unclear description Not source
Lost files Unable to decompress Bad
*Content ：
*Captcha :
DSSZ is the largest source code store in internet!
Contact us :
1999-2046 DSSZ All Rights Reserved.