ynthesizable FIR filters in VHDL with a focus on optimal mapping to Xilinx DSP slices. This repository contains a transposed direct form, systolic form for single-rate FIR filters and a custom parallel polyphase FIR decimating filter. The VHDL has been synthesized with Xilinx Vivado 2015.1 to confirm the correct DSP cascade chain is inferred.

Filename	Size	Update
VHDL-FIR-filters-master	0	2016-06-02
VHDL-FIR-filters-master\LICENSE	11358	2016-06-02
VHDL-FIR-filters-master\README.md	426	2016-06-02
VHDL-FIR-filters-master\deps	0	2016-06-02
VHDL-FIR-filters-master\deps\standard_additions_c.vhdl	61419	2016-06-02
VHDL-FIR-filters-master\src	0	2016-06-02
VHDL-FIR-filters-master\src\CoeffHelpers.vhd	992	2016-06-02
VHDL-FIR-filters-master\src\FIR_DirectTranspose.vhd	3458	2016-06-02
VHDL-FIR-filters-master\src\FIR_Systolic.vhd	2562	2016-06-02
VHDL-FIR-filters-master\src\ParallelPolyphase.vhd	979	2016-06-02
VHDL-FIR-filters-master\test	0	2016-06-02
VHDL-FIR-filters-master\test\FIR_tb.vhd	3139	2016-06-02
VHDL-FIR-filters-master\test\FIR_tb_behav.wcfg	4061	2016-06-02
VHDL-FIR-filters-master\test\ParallelPolyphase_tb.vhd	1175	2016-06-02
VHDL-FIR-filters-master\test\TestVectors.vhd	40730	2016-06-02

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