DDC中的抽取滤波器设计及FPGA实现 In this paper, the decimation

DDC中的抽取滤波器设计及FPGA实现

Category : VHDL-FPGA-Verilog
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Update : 2017-10-07
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Author ：davidbmd
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In this paper, the decimation filtering in the down conversion module is analyzed in detail, and the realization process and method of FPGA are discussed in detail

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DDC中的抽取滤波器设计及FPGA实现.pdf

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