UART16550 compatible serial communication controller, Verilog language description, the use of Altera Cyclone series FPGA chip integrated, as part of the use of FIFO to the internal resources to achieve. Projects have been in a successful application, is hereby introduced.

Packet : 11118676616550.rar filelist
timescale.v
uart_core.v
uart_defines.v
uart_in.v
uart_out.v
uart_recv.v
uart_send.v
uart_top.v

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