The RAM is based on the SystemC language and provides register initial values for testing.

SC_LAB 4_2RAM
SC_LAB 4_2RAM\.vs
SC_LAB 4_2RAM\.vs\SC_LAB 4_2RAM
SC_LAB 4_2RAM\.vs\SC_LAB 4_2RAM\v14
SC_LAB 4_2RAM\.vs\SC_LAB 4_2RAM\v14\.suo
SC_LAB 4_2RAM\Debug
SC_LAB 4_2RAM\Debug\SC_LAB 4_2RAM.exe
SC_LAB 4_2RAM\Debug\SC_LAB 4_2RAM.ilk
SC_LAB 4_2RAM\Debug\SC_LAB 4_2RAM.pdb
SC_LAB 4_2RAM\SC_LAB 4_2RAM
SC_LAB 4_2RAM\SC_LAB 4_2RAM.sdf
SC_LAB 4_2RAM\SC_LAB 4_2RAM.sln
SC_LAB 4_2RAM\SC_LAB 4_2RAM\Debug
SC_LAB 4_2RAM\SC_LAB 4_2RAM\Debug\main.obj
SC_LAB 4_2RAM\SC_LAB 4_2RAM\Debug\ram.obj
SC_LAB 4_2RAM\SC_LAB 4_2RAM\Debug\SC_LAB 4_2RAM.Build.CppClean.log
SC_LAB 4_2RAM\SC_LAB 4_2RAM\Debug\SC_LAB 4_2RAM.log
SC_LAB 4_2RAM\SC_LAB 4_2RAM\Debug\SC_LAB 4_2RAM.tlog
SC_LAB 4_2RAM\SC_LAB 4_2RAM\Debug\SC_LAB 4_2RAM.tlog\CL.read.1.tlog
SC_LAB 4_2RAM\SC_LAB 4_2RAM\Debug\SC_LAB 4_2RAM.tlog\CL.write.1.tlog
SC_LAB 4_2RAM\SC_LAB 4_2RAM\Debug\SC_LAB 4_2RAM.tlog\link.read.1.tlog
SC_LAB 4_2RAM\SC_LAB 4_2RAM\Debug\SC_LAB 4_2RAM.tlog\link.write.1.tlog
SC_LAB 4_2RAM\SC_LAB 4_2RAM\Debug\SC_LAB 4_2RAM.tlog\SC_LAB 4_2RAM.lastbuildstate
SC_LAB 4_2RAM\SC_LAB 4_2RAM\Debug\source.obj
SC_LAB 4_2RAM\SC_LAB 4_2RAM\Debug\testbench.obj
SC_LAB 4_2RAM\SC_LAB 4_2RAM\Debug\vc140.idb
SC_LAB 4_2RAM\SC_LAB 4_2RAM\Debug\vc140.pdb
SC_LAB 4_2RAM\SC_LAB 4_2RAM\main.cpp
SC_LAB 4_2RAM\SC_LAB 4_2RAM\ram.cpp
SC_LAB 4_2RAM\SC_LAB 4_2RAM\ram.h
SC_LAB 4_2RAM\SC_LAB 4_2RAM\SC_LAB 4_2RAM.vcxproj
SC_LAB 4_2RAM\SC_LAB 4_2RAM\SC_LAB 4_2RAM.vcxproj.filters
SC_LAB 4_2RAM\SC_LAB 4_2RAM\source.cpp
SC_LAB 4_2RAM\SC_LAB 4_2RAM\T1.txt
SC_LAB 4_2RAM\SC_LAB 4_2RAM\testbench.cpp
SC_LAB 4_2RAM\SC_LAB 4_2RAM\testbench.h

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