Verilog prepared by the DDS-based signal generator, the frequency variable.

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dds_synthesizer\trunk\doc\dds_synthesizer.pdf
dds_synthesizer\trunk\doc\dds_synthesizer.tex
dds_synthesizer\trunk\doc\images\build.sh
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dds_synthesizer\trunk\doc\images\dds_implementation.pdf
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dds_synthesizer\trunk\matlab\generate_vhdl_lut.m
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dds_synthesizer\trunk\matlab\sine_lut_gen.m
dds_synthesizer\trunk\sim\dds_synthesizer.cr.mti
dds_synthesizer\trunk\sim\dds_synthesizer.mpf
dds_synthesizer\trunk\sim\transcript
dds_synthesizer\trunk\sim\vsim.wlf
dds_synthesizer\trunk\sim\WAVEFORMS\dds_synthesizer.do
dds_synthesizer\trunk\vhdl\dds_synthesizer.vhd
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dds_synthesizer\trunk\vhdl\sine_lut\sine_lut_10_x_14.vhd
dds_synthesizer\trunk\vhdl\sine_lut\sine_lut_10_x_16.vhd
dds_synthesizer\trunk\vhdl\sine_lut\sine_lut_10_x_8.vhd
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dds_synthesizer\trunk\vhdl\sine_lut\sine_lut_12_x_14.vhd
dds_synthesizer\trunk\vhdl\sine_lut\sine_lut_12_x_16.vhd
dds_synthesizer\trunk\vhdl\sine_lut\sine_lut_12_x_8.vhd
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dds_synthesizer\trunk\vhdl\sine_lut\sine_lut_14_x_16.vhd
dds_synthesizer\trunk\vhdl\sine_lut\sine_lut_14_x_8.vhd
dds_synthesizer\trunk\vhdl\sine_lut\sine_lut_16_x_10.vhd
dds_synthesizer\trunk\vhdl\sine_lut\sine_lut_16_x_12.vhd
dds_synthesizer\trunk\vhdl\sine_lut\sine_lut_16_x_14.vhd
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dds_synthesizer\trunk\vhdl\sine_lut\sine_lut_16_x_8.vhd
dds_synthesizer\trunk\vhdl\sine_lut\sine_lut_8_x_10.vhd
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dds_synthesizer\trunk\vhdl\sine_lut\sine_lut_8_x_16.vhd
dds_synthesizer\trunk\vhdl\sine_lut\sine_lut_8_x_8.vhd
dds_synthesizer\web_uploads\dds_implementation.png
dds_synthesizer\web_uploads\thumb_dds_implementation.png
dds_synthesizer\trunk\doc\images
dds_synthesizer\trunk\sim\WAVEFORMS
dds_synthesizer\trunk\vhdl\sine_lut
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dds_synthesizer\trunk\matlab
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dds_synthesizer\trunk\vhdl
dds_synthesizer\branches
dds_synthesizer\tags
dds_synthesizer\trunk
dds_synthesizer\web_uploads
dds_synthesizer

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