Embedded serial communication, written using Verilog, altera development board on the run

uart\db\altsyncram_mnf1.tdf
uart\db\a_dpfifo_6q71.tdf
uart\db\cmpr_hs8.tdf
uart\db\cntr_9a7.tdf
uart\db\cntr_s9b.tdf
uart\db\cntr_t9b.tdf
uart\db\logic_util_heursitic.dat
uart\db\prev_cmp_uart.qmsg
uart\db\scfifo_vj71.tdf
uart\db\uart.amm.cdb
uart\db\uart.asm.qmsg
uart\db\uart.asm.rdb
uart\db\uart.cbx.xml
uart\db\uart.cmp.bpm
uart\db\uart.cmp.cdb
uart\db\uart.cmp.hdb
uart\db\uart.cmp.kpt
uart\db\uart.cmp.logdb
uart\db\uart.cmp.rdb
uart\db\uart.cmp_merge.kpt
uart\db\uart.cycloneive_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
uart\db\uart.cycloneive_io_sim_cache.31um_ss_1200mv_0c_slow.hsd
uart\db\uart.cycloneive_io_sim_cache.31um_ss_1200mv_85c_slow.hsd
uart\db\uart.db_info
uart\db\uart.fit.qmsg
uart\db\uart.hier_info
uart\db\uart.hif
uart\db\uart.idb.cdb
uart\db\uart.lpc.html
uart\db\uart.lpc.rdb
uart\db\uart.lpc.txt
uart\db\uart.map.bpm
uart\db\uart.map.cdb
uart\db\uart.map.hdb
uart\db\uart.map.kpt
uart\db\uart.map.logdb
uart\db\uart.map.qmsg
uart\db\uart.map_bb.cdb
uart\db\uart.map_bb.hdb
uart\db\uart.map_bb.logdb
uart\db\uart.pre_map.cdb
uart\db\uart.pre_map.hdb
uart\db\uart.rpp.qmsg
uart\db\uart.rtlv.hdb
uart\db\uart.rtlv_sg.cdb
uart\db\uart.rtlv_sg_swap.cdb
uart\db\uart.sgate.rvd
uart\db\uart.sgate_sm.rvd
uart\db\uart.sgdiff.cdb
uart\db\uart.sgdiff.hdb
uart\db\uart.sld_design_entry.sci
uart\db\uart.sld_design_entry_dsc.sci
uart\db\uart.smart_action.txt
uart\db\uart.sta.qmsg
uart\db\uart.sta.rdb
uart\db\uart.syn_hier_info
uart\db\uart.tis_db_list.ddb
uart\db\uart.tmw_info
uart\greybox_tmp\cbx_args.txt
uart\incremental_db\compiled_partitions\uart.db_info
uart\incremental_db\compiled_partitions\uart.root_partition.cmp.cdb
uart\incremental_db\compiled_partitions\uart.root_partition.cmp.dfp
uart\incremental_db\compiled_partitions\uart.root_partition.cmp.hdb
uart\incremental_db\compiled_partitions\uart.root_partition.cmp.kpt
uart\incremental_db\compiled_partitions\uart.root_partition.cmp.logdb
uart\incremental_db\compiled_partitions\uart.root_partition.cmp.rcfdb
uart\incremental_db\compiled_partitions\uart.root_partition.map.cdb
uart\incremental_db\compiled_partitions\uart.root_partition.map.dpi
uart\incremental_db\compiled_partitions\uart.root_partition.map.hbdb.cdb
uart\incremental_db\compiled_partitions\uart.root_partition.map.hbdb.hb_info
uart\incremental_db\compiled_partitions\uart.root_partition.map.hbdb.hdb
uart\incremental_db\compiled_partitions\uart.root_partition.map.hbdb.sig
uart\incremental_db\compiled_partitions\uart.root_partition.map.hdb
uart\incremental_db\compiled_partitions\uart.root_partition.map.kpt
uart\incremental_db\README
uart\rx_fifo_module.qip
uart\source\detect_module.v
uart\source\inter_control_module.v
uart\source\rx_bps_module.v
uart\source\rx_bps_module.v.bak
uart\source\rx_control_module.v
uart\source\rx_fifo_module.qip
uart\source\rx_fifo_module.v
uart\source\rx_fifo_module_bb.v
uart\source\rx_fifo_module_inst.v
uart\source\rx_interface.v
uart\source\rx_module.v
uart\source\rx_top_control_module.v
uart\source\rx_tx_interface_demo.v
uart\source\tx_bps_module.v
uart\source\tx_bps_module.v.bak
uart\source\tx_control_module.v
uart\source\tx_fifo_module.qip
uart\source\tx_fifo_module.v
uart\source\tx_fifo_module_bb.v
uart\source\tx_fifo_module_inst.v
uart\source\tx_interface.v
uart\source\tx_module.v
uart\source\tx_top_control_module.v
uart\tcl\18_osh.tcl

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