Use verilog language to achieve altera under the cycloneII series FPGA on-chip ROM to create, read and write, call IP core

12.ROM\db\logic_util_heursitic.dat
......\..\prev_cmp_rom.qmsg
......\..\rom.cbx.xml
......\..\rom.cmp.rdb
......\..\rom.db_info
......\..\rom.eco.cdb
......\..\rom.hif
......\..\rom.ipinfo
......\..\rom.map.qmsg
......\..\rom.map.rdb
......\..\rom.map_bb.hdb
......\..\rom.pti_db_list.ddb
......\..\rom.sld_design_entry.sci
......\..\rom.smart_action.txt
......\..\rom.tis_db_list.ddb
......\greybox_tmp\cbx_args.txt
......\my_rom.v
......\my_rom.v.bak
......\output_files\rom.flow.rpt
......\............\rom.map.rpt
......\............\rom.map.smsg
......\............\rom.map.summary
......\rom.mif
......\rom.pti_db_list.ddb
......\rom.qip
......\rom.qpf
......\rom.qsf
......\rom.qws
......\rom.tis_db_list.ddb
......\rom.v
......\rom.v.bak
......\romm.v
......\rom_inst.v
......\rom_inst.v.bak
......\db
......\greybox_tmp
......\output_files
12.ROM

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