here I send VHDL code for IDEA algorithm

xilinx-idea-vhdl-master
.......................\README.md
.......................\adder.vhd
.......................\bit_register.vhd
.......................\clk_div.vhd
.......................\clockedround.vhd
.......................\control.vhd
.......................\datapath.vhd
.......................\idea.vhd
.......................\idea_com.vhd
.......................\idea_com_inner.vhd
.......................\idea_com_scheduling.prj
.......................\idea_scheduling.vhd
.......................\idea_single.vhd
.......................\isim.cmd
.......................\isim.log
.......................\keygenerator.vhd
.......................\modulo-multiplier.vhd
.......................\multiplexer.vhd
.......................\quadmultiplex.vhd
.......................\round.vhd
.......................\roundcontroller.vhd
.......................\roundcounter.vhd
.......................\rxcver.vhd
.......................\tb_addop.vhd
.......................\tb_bit_register.vhd
.......................\tb_clockedround2.vhd
.......................\tb_control.vhd
.......................\tb_idea.vhd
.......................\tb_idea_scheduling.vhd
.......................\tb_idea_single.vhd
.......................\tb_keygenerator.vhd
.......................\tb_mulop.vhd
.......................\tb_multiplexer.vhd
.......................\tb_quadmultiplexer.vhd
.......................\tb_round.vhd
.......................\tb_roundcontrollerT.vhd
.......................\tb_roundcounter.vhd
.......................\tb_trafo.vhd
.......................\tb_xorop.vhd
.......................\trafo.vhd
.......................\txmit.vhd
.......................\uart.vhd
.......................\xorop.vhd

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