To learn the Verilog design for ALU and Register Files which are two main building blocks of a CPU.

ALU and Register File\ALU + RF datapath\ALU.v
.....................\.................\DP.v
.....................\.................\DP_tb.v
.....................\.................\RF_256x32.v
.....................\.rithmetic Logic Unit (ALU)\ALU.v
.....................\...........................\ALU_tb.v
.....................\Register File (RF)\RF_256x32.v
.....................\..................\RF_256x32_tb.v
.....................\Serial-in parallel-out register file\SPRF_64x8.v
.....................\....................................\SPRF_64x8_tb.v
.....................\ALU + RF datapath
.....................\Arithmetic Logic Unit (ALU)
.....................\Register File (RF)
.....................\Serial-in parallel-out register file
ALU and Register File

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