Full adder VHDL-based program, with gates to achieve two binary numbers together and find a combination of lines and is seeking the binary vector addition.

qjq\qjq.qpf
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...\db\qjq.cmp.rdb
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...\..\qjq.lpc.txt
...\..\qjq.fit.qmsg
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...\..\qjq.sta.qmsg
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...\..............\README
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...\sim\qjq.vht
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...\...\qjq_modelsim.xrf
...\...\qjq.vho
...\...\qjq_fast.vho
...\...\qjq_vhd.sdo
...\...\qjq_vhd_fast.sdo
...\...\qjq_run_msim_gate_vhdl.do
...\...\gate_work\_info
...\...\.........\_vmake
...\...\.........\qjq\_primary.dbs
...\...\.........\...\_primary.dat
...\...\.........\...\structure.dbs
...\...\.........\...\structure.dat
...\...\.........\...\structure.psm
...\...\.........\...\structure.prw
...\...\qjq.sft
...\...\qjq_run_msim_rtl_vhdl.do
...\...\msim_transcript
...\...\rtl_work\_info
...\...\........\_vmake
...\...\........\qjq\_primary.dbs

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