Achieve any clock divider, simple, open modelsim-change directroy-do sim. Do to

work\sim\modelsim.ini
....\...\sim.do
....\...\sim.do.bak
....\...\vsim.wlf
....\...\wave.do
....\...\wave.do.wlf
....\...\.ork\div_clk\verilog.asm
....\...\....\.......\verilog.rw
....\...\....\.......\_primary.dat
....\...\....\.......\_primary.dbs
....\...\....\.......\_primary.vhd
....\...\....\tb_div_clk\verilog.asm
....\...\....\..........\verilog.rw
....\...\....\..........\_primary.dat
....\...\....\..........\_primary.dbs
....\...\....\..........\_primary.vhd
....\...\....\_info
....\...\....\.temp\vlog01ywqq
....\...\....\.....\vlog02r1rb
....\...\....\.....\vlog1s1c8d
....\...\....\.....\vlog2q5gtd
....\...\....\.....\vlog2qf01e
....\...\....\.....\vlog34h7wx
....\...\....\.....\vlog5zna2g
....\...\....\.....\vlog7hzvm4
....\...\....\.....\vlogb16mmk
....\...\....\.....\vlogbajaxd
....\...\....\.....\vlogi1i97x
....\...\....\.....\vlogjic357
....\...\....\.....\vlogk8ydvd
....\...\....\.....\vlogkhxk6v
....\...\....\.....\vlogmvs3z7
....\...\....\.....\vlogr362xv
....\...\....\.....\vlogrzc3x9
....\...\....\.....\vlogsq4ez4
....\...\....\.....\vlogwwnhtg
....\...\....\.....\vlogyib26n
....\...\....\_vmake
....\.rc\div.V.bak
....\...\div_clk.V
....\tb\tb_div.v.bak
....\..\tb_div_clk.v
....\..\tb_div_clk.v.bak
....\sim\work\div_clk
....\...\....\tb_div_clk
....\...\....\_temp
....\...\work
....\sim
....\src
....\tb
work

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