This is the module on the VHDL source code, welcomed the U.S. download.

Packet : 109201269vhdl_block.rar filelist
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\cmp_state.ini
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\counter_10.vhd
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\counter_ctrl.vhd
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\db\add_sub_1sh.tdf
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\db\frequency_counter_2.(0).cnf.cdb
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\db\frequency_counter_2.(0).cnf.hdb
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\db\frequency_counter_2.(1).cnf.cdb
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\db\frequency_counter_2.(1).cnf.hdb
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\db\frequency_counter_2.(2).cnf.cdb
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\db\frequency_counter_2.(2).cnf.hdb
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\db\frequency_counter_2.(3).cnf.cdb
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\db\frequency_counter_2.(3).cnf.hdb
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\db\frequency_counter_2.cbx.xml
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\db\frequency_counter_2.cmp.rdb
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\db\frequency_counter_2.db_info
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\db\frequency_counter_2.eco.cdb
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\db\frequency_counter_2.eds_overflow
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\db\frequency_counter_2.fnsim.cdb
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\db\frequency_counter_2.fnsim.hdb
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\db\frequency_counter_2.hier_info
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\db\frequency_counter_2.hif
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\db\frequency_counter_2.map.cdb
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\db\frequency_counter_2.map.hdb
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\db\frequency_counter_2.map.logdb
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\db\frequency_counter_2.map.qmsg
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\db\frequency_counter_2.pre_map.cdb
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\db\frequency_counter_2.pre_map.hdb
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\db\frequency_counter_2.psp
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\db\frequency_counter_2.rpp.qmsg
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\db\frequency_counter_2.rtlv.hdb
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\db\frequency_counter_2.rtlv_sg.cdb
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\db\frequency_counter_2.rtlv_sg_swap.cdb
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\db\frequency_counter_2.sgate.rvd
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\db\frequency_counter_2.sgdiff.cdb
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\db\frequency_counter_2.sgdiff.hdb
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\db\frequency_counter_2.sim.hdb
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\db\frequency_counter_2.sim.qmsg
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\db\frequency_counter_2.sim.rdb
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\db\frequency_counter_2.sim.vwf
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\db\frequency_counter_2.sld_design_entry.sci
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\db\frequency_counter_2.sld_design_entry_dsc.sci
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\db\frequency_counter_2.syn_hier_info
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\db\frequency_counter_2_cmp.qrpt
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\db\frequency_counter_2_sim.qrpt
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\frequency_counter_2.done
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\frequency_counter_2.flow.rpt
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\frequency_counter_2.map.eqn
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\frequency_counter_2.map.rpt
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\frequency_counter_2.map.summary
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\frequency_counter_2.qpf
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\frequency_counter_2.qsf
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\frequency_counter_2.qws
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\frequency_counter_2.sim.rpt
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\frequency_counter_2.vhd
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\frequency_counter_2.vwf
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\package_counter.vhd
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\reg_32bit.vhd
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)\db
调用底层VHDL模块\frequency_counter_2(successful)(top-down design)
调用底层VHDL模块

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