EDA software platform based on the hardware description language verilog design complete shift of the frequency divider, timer, serial output, pseudo-code generator, the QPSK the I/Q modulator, QPSK I/Q demodulator based option law IF modulator, and then the individual modules together to form a complete system simulation and its quartusII software.

cshiyan2012
...........\QPSK_module.asm.rpt
...........\QPSK_module.bsf
...........\QPSK_module.done
...........\QPSK_module.eda.rpt
...........\QPSK_module.fit.rpt
...........\QPSK_module.fit.smsg
...........\QPSK_module.fit.summary
...........\QPSK_module.flow.rpt
...........\QPSK_module.map.rpt
...........\QPSK_module.map.summary
...........\QPSK_module.pin
...........\QPSK_module.qpf
...........\QPSK_module.qsf
...........\QPSK_module.qws
...........\QPSK_module.sim.rpt
...........\QPSK_module.tan.rpt
...........\QPSK_module.tan.summary
...........\QPSK_module.v
...........\QPSK_module.v.bak
...........\QPSK_module.vwf
...........\Waveform1.vwf
...........\cshiyan2012.asm.rpt
...........\cshiyan2012.bdf
...........\cshiyan2012.done
...........\cshiyan2012.fit.rpt
...........\cshiyan2012.fit.smsg
...........\cshiyan2012.fit.summary
...........\cshiyan2012.flow.rpt
...........\cshiyan2012.map.rpt
...........\cshiyan2012.map.summary
...........\cshiyan2012.pin
...........\cshiyan2012.qpf
...........\cshiyan2012.qsf
...........\cshiyan2012.qws
...........\cshiyan2012.sim.rpt
...........\cshiyan2012.tan.rpt
...........\cshiyan2012.tan.summary
...........\cshiyan2012.vwf
...........\cshiyan2012_assignment_defaults.qdf
...........\db
...........\..\QPSK_module.asm.qmsg
...........\..\QPSK_module.cbx.xml
...........\..\QPSK_module.cmp.bpm
...........\..\QPSK_module.cmp.cdb
...........\..\QPSK_module.cmp.ecobp
...........\..\QPSK_module.cmp.hdb
...........\..\QPSK_module.cmp.logdb
...........\..\QPSK_module.cmp.rdb
...........\..\QPSK_module.cmp.tdb
...........\..\QPSK_module.cmp0.ddb
...........\..\QPSK_module.cmp2.ddb
...........\..\QPSK_module.db_info
...........\..\QPSK_module.eco.cdb
...........\..\QPSK_module.eda.qmsg
...........\..\QPSK_module.eds_overflow
...........\..\QPSK_module.fit.qmsg
...........\..\QPSK_module.fnsim.cdb
...........\..\QPSK_module.fnsim.hdb
...........\..\QPSK_module.fnsim.qmsg
...........\..\QPSK_module.hier_info
...........\..\QPSK_module.hif
...........\..\QPSK_module.map.bpm
...........\..\QPSK_module.map.cdb
...........\..\QPSK_module.map.ecobp
...........\..\QPSK_module.map.hdb
...........\..\QPSK_module.map.logdb
...........\..\QPSK_module.map.qmsg
...........\..\QPSK_module.map_bb.cdb
...........\..\QPSK_module.map_bb.hdb
...........\..\QPSK_module.map_bb.hdbx
...........\..\QPSK_module.map_bb.logdb
...........\..\QPSK_module.pre_map.cdb
...........\..\QPSK_module.pre_map.hdb
...........\..\QPSK_module.psp
...........\..\QPSK_module.root_partition.cmp.atm
...........\..\QPSK_module.root_partition.cmp.dfp
...........\..\QPSK_module.root_partition.cmp.hdbx
...........\..\QPSK_module.root_partition.cmp.logdb
...........\..\QPSK_module.root_partition.cmp.rcf
...........\..\QPSK_module.root_partition.map.atm
...........\..\QPSK_module.root_partition.map.hdbx
...........\..\QPSK_module.root_partition.map.info
...........\..\QPSK_module.rtlv.hdb
...........\..\QPSK_module.rtlv_sg.cdb
...........\..\QPSK_module.rtlv_sg_swap.cdb
...........\..\QPSK_module.sgdiff.cdb
...........\..\QPSK_module.sgdiff.hdb
...........\..\QPSK_module.signalprobe.cdb
...........\..\QPSK_module.sim.cvwf
...........\..\QPSK_module.sim.hdb
...........\..\QPSK_module.sim.qmsg
...........\..\QPSK_module.sim.rdb
...........\..\QPSK_module.simfam
...........\..\QPSK_module.sld_design_entry.sci
...........\..\QPSK_module.sld_design_entry_dsc.sci
...........\..\QPSK_module.syn_hier_info
...........\..\QPSK_module.tan.qmsg
...........\..\QPSK_module.tis_db_list.ddb
...........\..\QPSK_module.tmw_info

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