Introduction - If you have any usage issues, please Google them yourself
To the designers of some of the information, to engage in FPGA design can also take a look at my friends, absorbing a little experience,
Packet : 47651469jtag.rar filelist
jtag\tap\doc\jtag.pdf
jtag\tap\doc\src\jtag.doc
jtag\tap\doc\src
jtag\tap\doc
jtag\tap\rtl\verilog\tap_defines.v
jtag\tap\rtl\verilog\tap_top.v
jtag\tap\rtl\verilog
jtag\tap\rtl
jtag\tap
jtag