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  • Update : 2008-10-13
  • Size : 1.59mb
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  • Author :gexiaowei
  • About : gexiaowei
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Introduction - If you have any usage issues, please Google them yourself
I produced eight CPU, has a simple addition and subtraction, input and output operations, I hope everyone use
Packet file list
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Packet : 119128669cpu.rar filelist
80386.zip
IT51_src[1].tar.gz
openrisc1200\or1k\or1200\CVS\Root
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openrisc1200\or1k\or1200\rtl\verilog\or1200_amultp2_32x32.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_cfgr.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_cpu.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_ctrl.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_dc_fsm.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_dc_ram.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_dc_tag.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_dc_top.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_defines.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_dmmu_tlb.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_dmmu_top.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_dpram_256x32.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_dpram_32x32.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_du.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_except.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_freeze.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_genpc.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_gmultp2_32x32.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_ic_fsm.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_ic_ram.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_ic_tag.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_ic_top.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_if.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_immu_tlb.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_immu_top.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_iwb_biu.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_lsu.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_mem2reg.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_mult_mac.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_operandmuxes.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_pic.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_pm.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_qmem_top.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_reg2mem.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_rf.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_rfram_generic.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_sb.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_sb_fifo.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_spram_1024x32.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_spram_1024x32_bw.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_spram_1024x8.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_spram_128x32.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_spram_2048x32.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_spram_2048x32_bw.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_spram_2048x8.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_spram_256x21.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_spram_32x24.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_spram_512x20.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_spram_64x14.v
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openrisc1200\or1k\or1200\rtl\verilog\or1200_spram_64x24.v
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openrisc1200\or1k\or1200\rtl\verilog\or1200_tpram_32x32.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_tt.v
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openrisc1200\or1k\or1200\rtl\verilog\or1200_xcv_ram32x8d.v
openrisc1200\or1k\or1200\rtl\verilog\timescale.v
openrisc1200\or1k\or1200\rtl\verilog
openrisc1200\or1k\or1200\rtl
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openrisc1200\or1k\or1200\syn\synopsys\bin\read_design.inc
openrisc1200\or1k\or1200\syn\synopsys\bin\run_syn
openrisc1200\or1k\or1200\syn\synopsys\bin\top.scr
openrisc1200\or1k\or1200\syn\synopsys\bin
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openrisc1200\or1k\or1200
openrisc1200\or1k
openrisc1200
8051core-Verilog.zip
8088verilog.zip
8088vhdl.zip
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