Realize the pci interface

5.4
...\chart
...\.....\Thumbs.db
...\.....\图5-14.bmp
...\.....\图5-15.bmp
...\.....\表5-4(续1-1).bmp
...\.....\表5-4(续1-2).bmp
...\.....\表5-4(续2).bmp
...\.....\表5-4.bmp
...\modelsim.ini
...\note.txt
...\pci.cr.mti
...\pci.mpf
...\pci_tb.v
...\state_machine.v
...\transcript
...\vsim.wlf
...\wave
...\....\pci_tb.bmp
...\....\state_machine.bmp
...\....\Thumbs.db
...\work
...\....\base_addr_chk
...\....\.............\verilog.asm
...\....\.............\_primary.dat
...\....\.............\_primary.vhd
...\....\bkend_daemon
...\....\............\verilog.asm
...\....\............\_primary.dat
...\....\............\_primary.vhd
...\....\config_mux
...\....\..........\verilog.asm
...\....\..........\_primary.dat
...\....\..........\_primary.vhd
...\....\glue
...\....\....\verilog.asm
...\....\....\_primary.dat
...\....\....\_primary.vhd
...\....\pargen
...\....\......\verilog.asm
...\....\......\_primary.dat
...\....\......\_primary.vhd
...\....\pci_clk_reset
...\....\.............\verilog.asm
...\....\.............\_primary.dat
...\....\.............\_primary.vhd
...\....\pci_stim
...\....\........\verilog.asm
...\....\........\_primary.dat
...\....\........\_primary.vhd
...\....\pci_tb
...\....\......\verilog.asm
...\....\......\_primary.dat
...\....\......\_primary.vhd
...\....\pci_top
...\....\.......\verilog.asm
...\....\.......\_primary.dat
...\....\.......\_primary.vhd
...\....\retry_count
...\....\...........\verilog.asm
...\....\...........\_primary.dat
...\....\...........\_primary.vhd
...\....\state_machine
...\....\.............\verilog.asm
...\....\.............\_primary.dat
...\....\.............\_primary.vhd
...\....\_info

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