• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on Altera’s UP2 board are included in “Quartus UP2 Designs.zip” • The OVL directory has OVL library version 1.0 and its documentations • In the Software directory, the Altera directory contains Quartus II, related tools, and Altera device specifications. Please connect to www.altera.com and then click on “University Program” to obtain a license for Quartus II Web Edition. • In the Software directory, The MentorGraphics directory has the ModelSim-Altera simulation program. Please connect to www.altera.com and then click on “University Program” to obtain a license for ModelSim-Altera.

Chapter 3\Flipflop.v
.........\FlipflopAssign.v
.........\FlipflopAssignTester.v
.........\FlipflopTester.v
.........\Fulladder.v
.........\FulladderTester.v
.........\MemoryTest.v
.........\Mux2ti1TestA.v
.........\Mux2to1.v
.........\Mux2to1BTest.v
.........\Mux2to1Multiple.v
.........\Mux2to1Net.v
.........\Mux2to1TestC.v
.........\Mux2to1Tester.v
.........\NumberTest.v
.........\OperatorTest.v
.........\SignTest.v
Chapter 3

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