Verilog implementation of AES

version 2\AES.mpf
.........\cipher_128.v
.........\inverse.v
.........\keyGen_256.v
.........\keyModule.v
.........\keyRAM.v
.........\keyRAM_128.v
.........\mixColumn_128.v
.........\mixColumnByte.v
.........\mixColumnWord.v
.........\multiply.v
.........\power.v
.........\rcon.v
.........\reg_32.v
.........\sboxByte.v
.........\sboxWord.v
.........\shiftSubByte_128.v
.........\test.v
.........\xtime.v
.........\AES256_CORE.v
.........\AES256_CU.v
.........\AES256_DU.v
version 2

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